riscv vs biriscv

riscv

RISC-V CPU Core (RV32IM) (by ultraembedded)

#risc-v #Cpu #Verilog #Fpga #Verilator #Rv32im #Rv32i #riscv-linux #pipeline-processor #Asic #Verification

biriscv

32-bit Superscalar RISC-V CPU (by ultraembedded)

#risc-v #Rv32i #Rv32im #Superscalar #Cpu #Fpga #Verilog #pipelined-processors #Verilator #Coremark #Asic #branch-prediction #in-order #Linux #riscv-linux #Xilinx #artix-7

Source Code

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riscv		biriscv
	Project
1	Mentions	5
694	Stars	505
-	Growth	-
0.6	Activity	0.0
over 1 year ago	Latest Commit	over 1 year ago
Verilog	Language	Verilog
BSD 3-clause "New" or "Revised" License	License	Apache License 2.0

The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

riscv

Posts with mentions or reviews of riscv. We have used some of these posts to build our list of alternatives and similar projects.

We haven't tracked posts mentioning riscv yet.
Tracking mentions began in Dec 2020.

biriscv

Posts with mentions or reviews of biriscv. We have used some of these posts to build our list of alternatives and similar projects.

We haven't tracked posts mentioning biriscv yet.
Tracking mentions began in Dec 2020.

What are some alternatives?

When comparing riscv and biriscv you can also consider the following projects:

darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

sdspi - SD-Card controller, using a SPI interface that is (optionally) shared

zipcpu - A small, light weight, RISC CPU soft core

vgasim - A Video display simulator

ice40_power - Power analysis of the ICE40UP5K-SG48 devices

Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog

uhd - The USRP™ Hardware Driver Repository

wbicapetwo - Wishbone to ICAPE interface conversion

open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input