rust_hdl
hdl_checker
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| rust_hdl | hdl_checker | |
|---|---|---|
| 8 | 4 | |
| 298 | 183 | |
| 4.4% | - | |
| 9.3 | 0.0 | |
| 12 days ago | 4 months ago | |
| VHDL | Python | |
| GNU General Public License v3.0 or later | GNU General Public License v3.0 only |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
rust_hdl
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How to configure vim like an IDE
rust_hdl
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Free VHDL language server
I want to share a VHDL language server I have written in Rust. It is now in a really good state and is ready to be the daily driver for someone working on VHDL. It is completely free and open source, enjoy! https://github.com/VHDL-LS/rust_hdl
- Show HN: Fast VHDL language server written in Rust
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verilog-ext/vhdl-ext: SystemVerilog/VHDL extensions for Emacs
For VHDL, vhdl_ls seems to be the best choice for code navigation with support to find definitions and references as well as diagnostics. I do not know however how its internal linter compares to GHDL.
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Any better options than Sigasi?
I'm using emacs + rust_hdl as LSP and it provides me live-error-checking for VHDL designs. You should be able to use rust_hdl with any text editor of your choice as long as it supports LSP.
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Why is Vivado so crippingly slow?
In addition, install LSP mode (language server protocol) and run the https://github.com/VHDL-LS/rust_hdl rust hdl language server, that'll give you stuff like type hints for signals and ports etc.
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10 years into my career I would have bombed if I was asked FizzBuzz in an interview. My brain wasn't wired for that kind of problem, and yet I was still in the industry delivering value to employers for a decade.
Would this fix the problems or just delay the rottening process?
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What Editor is Everyone Using for FPGA design? (2021)
Same with rust_hdl as LSP.
hdl_checker
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Any better options than Sigasi?
I've written a LSP that uses modelsim, ghdl or Vivado to do error checking: https://github.com/suoto/hdl_checker
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What Editor is Everyone Using for FPGA design? (2021)
NeoVim + CoC + hdl_checker
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VHDL native lsp
As others mentioned, rust_hdl and ghdl ls are worth checking out. If your project has both VHDL and Verilog/SystemVerilog, might be worth checking https://github.com/suoto/hdl_checker (disclaimer, I'm the author). It's got less LS features than the other two but if you use it with modelsim it'll provide mixed language syntax check.
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IDE / Editor of choice
Specifically for HDL-files a lot of progress has been made in the last couple of years on lsp-mode and external LSP servers for code analysis of both VHDL and SystemVerilog. For SV I use the https://github.com/suoto/hdl_checker server that passes the code you are working on live to the Linting engine in Questa/ModelSim and marks the warning lines in the editor. It's nice to get immediate feedback on missing semicolons etc. although it still has a hard time handling large projects.
What are some alternatives?
ghdl - VHDL 2008/93/87 simulator
completor.vim - Async completion framework made ease.
nvim-tree.lua - A file explorer tree for neovim written in lua
veridian - A SystemVerilog Language Server
Terminal - Smally's very minimalistic dotfiles
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
verilog-ext - Verilog Extensions for Emacs
vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
AXI4 - AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
edalize - An abstraction library for interfacing EDA tools