rust_hdl
By VHDL-LS
AXI4
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components (by OSVVM)
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| rust_hdl | AXI4 | |
|---|---|---|
| 8 | 4 | |
| 298 | 101 | |
| 4.4% | - | |
| 9.3 | 7.5 | |
| 12 days ago | 19 days ago | |
| VHDL | VHDL | |
| GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
rust_hdl
Posts with mentions or reviews of rust_hdl.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-06-27.
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How to configure vim like an IDE
rust_hdl
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Free VHDL language server
I want to share a VHDL language server I have written in Rust. It is now in a really good state and is ready to be the daily driver for someone working on VHDL. It is completely free and open source, enjoy! https://github.com/VHDL-LS/rust_hdl
- Show HN: Fast VHDL language server written in Rust
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verilog-ext/vhdl-ext: SystemVerilog/VHDL extensions for Emacs
For VHDL, vhdl_ls seems to be the best choice for code navigation with support to find definitions and references as well as diagnostics. I do not know however how its internal linter compares to GHDL.
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Any better options than Sigasi?
I'm using emacs + rust_hdl as LSP and it provides me live-error-checking for VHDL designs. You should be able to use rust_hdl with any text editor of your choice as long as it supports LSP.
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Why is Vivado so crippingly slow?
In addition, install LSP mode (language server protocol) and run the https://github.com/VHDL-LS/rust_hdl rust hdl language server, that'll give you stuff like type hints for signals and ports etc.
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10 years into my career I would have bombed if I was asked FizzBuzz in an interview. My brain wasn't wired for that kind of problem, and yet I was still in the industry delivering value to employers for a decade.
Would this fix the problems or just delay the rottening process?
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What Editor is Everyone Using for FPGA design? (2021)
Same with rust_hdl as LSP.
AXI4
Posts with mentions or reviews of AXI4.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-02-02.
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I made an AXI introduction video! including an AXI-Lite master read and write example!
OSVVM also has an AXI4 VC/VIP. See https://github.com/OSVVM/OsvvmLibraries and for AXI4 specifically see: https://github.com/OSVVM/Axi4
- Reference of verification IPs
- Verilog Text Book Recommendations?
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Entity Input Ports
If you are looking for an AXI Subordinate (new AXI spec names) Memory, you may wish to look at the one from OSVVM (it is free open source (FOSS)). You will find it at: https://github.com/OSVVM/AXI4/blob/master/Axi4/src/Axi4Memory.vhd
What are some alternatives?
When comparing rust_hdl and AXI4 you can also consider the following projects:
hdl_checker - Repurposing existing HDL tools to help writing better code
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
ghdl - VHDL 2008/93/87 simulator
ravenoc - RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
nvim-tree.lua - A file explorer tree for neovim written in lua
spi-to-axi-bridge - An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
Terminal - Smally's very minimalistic dotfiles
spi-fpga - SPI master and SPI slave for FPGA written in VHDL
wb2axip - Bus bridges and other odds and ends
verilog-ext - Verilog Extensions for Emacs
forth-cpu - A Forth CPU and System on a Chip, based on the J1, written in VHDL