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rust_hdl | vunit | |
---|---|---|
8 | 10 | |
298 | 682 | |
4.4% | 2.1% | |
9.3 | 8.2 | |
12 days ago | 28 days ago | |
VHDL | VHDL | |
GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
rust_hdl
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How to configure vim like an IDE
rust_hdl
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Free VHDL language server
I want to share a VHDL language server I have written in Rust. It is now in a really good state and is ready to be the daily driver for someone working on VHDL. It is completely free and open source, enjoy! https://github.com/VHDL-LS/rust_hdl
- Show HN: Fast VHDL language server written in Rust
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verilog-ext/vhdl-ext: SystemVerilog/VHDL extensions for Emacs
For VHDL, vhdl_ls seems to be the best choice for code navigation with support to find definitions and references as well as diagnostics. I do not know however how its internal linter compares to GHDL.
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Any better options than Sigasi?
I'm using emacs + rust_hdl as LSP and it provides me live-error-checking for VHDL designs. You should be able to use rust_hdl with any text editor of your choice as long as it supports LSP.
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Why is Vivado so crippingly slow?
In addition, install LSP mode (language server protocol) and run the https://github.com/VHDL-LS/rust_hdl rust hdl language server, that'll give you stuff like type hints for signals and ports etc.
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10 years into my career I would have bombed if I was asked FizzBuzz in an interview. My brain wasn't wired for that kind of problem, and yet I was still in the industry delivering value to employers for a decade.
Would this fix the problems or just delay the rottening process?
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What Editor is Everyone Using for FPGA design? (2021)
Same with rust_hdl as LSP.
vunit
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Software languages vs HDLs for verification
My goto tools for verification in VHDL are UVVM and VUnit
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Libero - Inefficient Simulations
I think the VUnit vivado example (https://github.com/VUnit/vunit/tree/master/examples/vhdl/vivado) may be a good starting point when working with Xilinx IP outside of an IDE.
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Books About Testing and Verification
I learned a lot from https://vunit.github.io/ I even became a better VHDL engineer from this fantastic project. It showed me things I did not know VHDL was capable of.
- A couple of questions for the experts
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Reference of verification IPs
Hey! I haven't seen anyone mention Vunit yet. Vunit has a verification components library with Master and Slave components for a decent amount of buses: Axi, Axi stream, Wishbone, Avalon, Uart. The code isn't 100% bullet proof but it is really useful for testing designs.
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SystemVerilog testbench library
I agree vunit is great but due to circumstances (you can see post above) I need the testbench to be purely SV (and vunit as you said wouldn't help with all of that, only some of it, as you have pointed out). When I refered to vunit I forgot to link the example: https://github.com/VUnit/vunit/tree/master/examples/verilog/uart/src . I referred more to tge fact it is self checking, and the tasks can be reused in ither tbs as well
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The Vivado 2021.2 is out thread
As for simulation, the last time I used it there were a lot of features not supported. Not sure where this is documented, but I know VUnit can't support it per https://github.com/VUnit/vunit/issues/209 .
- How do you do automated testing of your HDL?
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VHDL Testbench Library Comparison
Please consider adding simulator support to this comparison. For example, Vivado's xsim can't be used with VUnit.
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The simplest way to automate my testbench?
I think these two examples can help you get started. https://github.com/VUnit/vunit/tree/master/examples/vhdl/array_axis_vcs https://github.com/VUnit/vunit/tree/master/examples/vhdl/generate_tests/
What are some alternatives?
hdl_checker - Repurposing existing HDL tools to help writing better code
spi-fpga - SPI master and SPI slave for FPGA written in VHDL
ghdl - VHDL 2008/93/87 simulator
AXI4 - AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
nvim-tree.lua - A file explorer tree for neovim written in lua
Terminal - Smally's very minimalistic dotfiles
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
verilog-ext - Verilog Extensions for Emacs
catapult-v3-smartnic-re - Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)
OsvvmLibraries - Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.