projf-explore
axi
projf-explore | axi | |
---|---|---|
3 | 3 | |
505 | 930 | |
1.8% | 3.0% | |
6.1 | 6.1 | |
3 months ago | 5 days ago | |
SystemVerilog | SystemVerilog | |
MIT License | GNU General Public License v3.0 or later |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
projf-explore
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Exploring FPGA Graphics
* https://github.com/projf/projf-explore/blob/main/graphics/fp...
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FPGA Advent Calendar
Twitter thread author here.
If this inspires you to learn more about FPGAs, check out:
1. Recommended FPGA Sites: https://projectf.io/recommended-fpga-sites/
2. Project F: https://projectf.io/sitemap/
3. Project F GitHub: https://github.com/projf/projf-explore
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Drawing with an FPGA
If you're interested in FPGA graphics, take a look at the latest version of the Project F Verilog library: https://github.com/projf/projf-explore/tree/master/lib/graphics.
axi
- AXI InterConnect
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Any recommendations for an RTL "standard library"?
Hi, I’m one of the developers of basejump. It’s pretty awesome, especially if you’re targeting ASIC. Nearly all the components have been through multiple advanced node tapeouts. The only weakness I see is a lack of AXI components. So I may suggest https://github.com/pulp-platform/axi to supplement
- How to compare HDL simulation/implementation results to Matlab?
What are some alternatives?
Cores-VeeR-EL2 - VeeR EL2 Core
chisel - Chisel: A Modern Hardware Design Language
fpga_craft - A voxel game/Minecraft clone for the iCE40 UP5K FPGA
nmigen - A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
eurorack-pmod - Hardware and gateware for getting started in FPGA-based audio synthesis with open source tools.
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
FPGA-Video-Processing - Realtime video processing w/ Gaussian + Sobel Filters targeting Artix-7 FPGA
opentitan - OpenTitan: Open source silicon root of trust
cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
qemu - Xilinx's fork of Quick EMUlator (QEMU) with improved support and modelling for the Xilinx platforms.
ndk-app-minimal - Minimal Application based on Network Development Kit (NDK) for FPGA cards
Pyverilog - Python-based Hardware Design Processing Toolkit for Verilog HDL