nestang
NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Primer 25K, Nano 20K and Primer 20K boards (by nand2mario)
darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night! (by darklife)
nestang | darkriscv | |
---|---|---|
5 | 3 | |
301 | 1,900 | |
- | 2.2% | |
8.5 | 6.3 | |
about 1 month ago | 26 days ago | |
SystemVerilog | Verilog | |
GNU General Public License v3.0 only | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
nestang
Posts with mentions or reviews of nestang.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-12-19.
- Gaming on less-expensive FPGAs?
- GitHub - nand2mario/nestang: NESTang is a Nintendo Entertainment System emulator on the affordable Sipeed Tang Primer 20K FPGA board.
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SiSpeed Tang Primer 20k and the programmer
I don't know if it's related to your dilemma, but this person reported having trouble uploading certain bitstreams.
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HDMI not showing up in IP Core Generator
You may want to take a look at nand2mario's NESTang project where they ported this open-source HDMI 1.4b core to Gowin hardware.
darkriscv
Posts with mentions or reviews of darkriscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-08-20.
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As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?
This guy here has designed his 2 stage RISC-V in just one right: https://github.com/darklife/darkriscv.
- Are there any dual-GBE, PoE-capable SBCs?
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Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.