neorv32
riscv-debug-dtm
| neorv32 | riscv-debug-dtm | |
|---|---|---|
| 77 | 3 | |
| 1,429 | 12 | |
| - | - | |
| 9.9 | 0.0 | |
| 7 days ago | over 1 year ago | |
| C | VHDL | |
| BSD 3-clause "New" or "Revised" License | BSD 3-clause "New" or "Revised" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
neorv32
- An example of how to add the A ISA extension's LR/SC operations into an open-source architecture
- NEORV32 - A tiny, customizable and highly extensible MCU-class 32-bit RISC-V microcontroller-like SoC written in platform-independent VHDL
-
Recommendations for RISC-V on FPGA
How about NEORV32?
-
SUGGEST AN OPEN SOURCE RISC-V CORE DESIGNED IN VERILOG
GitHub - stnolting/neorv32: 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. this one is good but is written in VHDL though
-
RISCV CPU using PL on Pynq Z2 Development Board
NEORV32 is an open source soft core and very well documented. I would recommend you to take a look at it and play around a bit. And it is certainly possible to have a soft core running on only the PL side without PS interference.
- A tiny 1-Wire controller for FPGAs (in VHDL)
-
Anyone want to share some embedded projects they have done?
Maybe not a classic (whatever that means...) project, but I am working (together with others) on a RISC-V microcontroller for FPGAs: https://github.com/stnolting/neorv32
riscv-debug-dtm
-
Input to FPGA
Here is a link to a JTAG Transport Module and some instructions how to read/write data words using OpenOCD: https://github.com/stnolting/riscv-debug-dtm
-
Looking for feedback on my most recent project (anything welcome)
just a brief readme: https://github.com/stnolting/riscv-debug-dtm
- Confused about the JTAG interface
What are some alternatives?
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
linux-on-litex-vexriscv - Linux on LiteX-VexRiscv
wb_spi_bridge - 🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).
picoMIPS - picoMIPS processor doing affine transformation
neorv32-riscof - ✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
lxp32-cpu - A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
fpga-zynq - Support for Rocket Chip on Zynq FPGAs
serv - SERV - The SErial RISC-V CPU
linux-on-litex-rocket - Run 64-bit Linux on LiteX + RocketChip