riscv-debug-dtm
🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification. (by stnolting)
wb_spi_bridge
🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP). (by stnolting)
| riscv-debug-dtm | wb_spi_bridge | |
|---|---|---|
| 3 | 2 | |
| 12 | 19 | |
| - | - | |
| 0.0 | 0.0 | |
| over 1 year ago | over 2 years ago | |
| VHDL | VHDL | |
| BSD 3-clause "New" or "Revised" License | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-debug-dtm
Posts with mentions or reviews of riscv-debug-dtm.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-09-21.
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Input to FPGA
Here is a link to a JTAG Transport Module and some instructions how to read/write data words using OpenOCD: https://github.com/stnolting/riscv-debug-dtm
-
Looking for feedback on my most recent project (anything welcome)
just a brief readme: https://github.com/stnolting/riscv-debug-dtm
- Confused about the JTAG interface
wb_spi_bridge
Posts with mentions or reviews of wb_spi_bridge.
We have used some of these posts to build our list of alternatives
and similar projects.
What are some alternatives?
When comparing riscv-debug-dtm and wb_spi_bridge you can also consider the following projects:
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
spi-to-axi-bridge - An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
neorv32-riscof - ✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
spi-fpga - SPI master and SPI slave for FPGA written in VHDL
sdram-fpga - A FPGA core for a simple SDRAM controller.