riscv-debug-dtm
neorv32-riscof
| riscv-debug-dtm | neorv32-riscof | |
|---|---|---|
| 3 | 2 | |
| 12 | 25 | |
| - | - | |
| 0.0 | 9.1 | |
| over 1 year ago | 3 days ago | |
| VHDL | Python | |
| BSD 3-clause "New" or "Revised" License | BSD 3-clause "New" or "Revised" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-debug-dtm
-
Input to FPGA
Here is a link to a JTAG Transport Module and some instructions how to read/write data words using OpenOCD: https://github.com/stnolting/riscv-debug-dtm
-
Looking for feedback on my most recent project (anything welcome)
just a brief readme: https://github.com/stnolting/riscv-debug-dtm
- Confused about the JTAG interface
neorv32-riscof
What are some alternatives?
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
fpga_puf - :key: Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
wb_spi_bridge - 🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).
fpu - IEEE 754 floating point library in system-verilog and vhdl
neorv32-setups - 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
potato - A simple RISC-V processor for use in FPGA designs.