naja
neorv32-verilog
| naja | neorv32-verilog | |
|---|---|---|
| 4 | 5 | |
| 43 | 39 | |
| - | - | |
| 9.0 | 8.1 | |
| 7 days ago | 2 days ago | |
| Python | Verilog | |
| Apache License 2.0 | BSD 3-clause "New" or "Revised" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
naja
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Naja-Verilog: stand-alone structural (gate-level) parser
Hi everyone, If you need to build C++ (or Python) application loading gate level verilog, similar to the one at the input of FPGA PnR tools, https://github.com/xtofalex/naja-verilog is available. This parser has been designed to allow the construction on the fly of any netlist data structure. One note: if you need also a C++ netlist data structure (with Python bindings) to build netlist analysis or editing tools on top, Naja SNL: https://github.com/xtofalex/naja is also ready for use. Hope this is useful. If it is or if you face any issue, please reach to me. Feedback welcome.
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Show HN: Naja-Verilog – Structural Verilog Parser
The project's other github repo is better to learn more about the project: https://github.com/xtofalex/naja
The linked repo doesn't have a informative Readme. An example showing showing Naja differs from existing tools would help people unfamiliar with Electronic Design Automation, like me.
- Naja - Open-source data structures for EDA back end tools development
- Show HN: Naja – open-source data structures for EDA back end tools development
neorv32-verilog
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Converting VHDL to Verilog using GHDL
I am not sure if this helps, but here is a project that also uses GHDL to convert a quite large VHDL setup (including package files) to Verilog: https://github.com/stnolting/neorv32-verilog
- Convert VHDL to Verilog using GHDL (using a RISC-V core as example)
- Show HN: Convert VHDL to Verilog using GHDL (+ first evaluation)
What are some alternatives?
naja-verilog - A standalone structural (gate-level) verilog parser
biriscv - 32-bit Superscalar RISC-V CPU
metron - A C++ to Verilog translation tool with some basic guarantees that your code will work.
riscv - RISC-V CPU Core (RV32IM)
verilator - Verilator open-source SystemVerilog simulator and lint system
serv - SERV - The SErial RISC-V CPU
rggen - Code generation tool for control and status registers
ghdl - VHDL 2008/93/87 simulator
Beagle_SDR_GPS - KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS
edalize - An abstraction library for interfacing EDA tools
fpga_floorplanning - NTHU CS5160 FPGA結構及設計自動化 麥偉基 Final Project