naja
Structural Netlist API (and more) for EDA post synthesis flow development (by najaeda)
verilator
Verilator open-source SystemVerilog simulator and lint system (by verilator)
| naja | verilator | |
|---|---|---|
| 4 | 12 | |
| 43 | 2,128 | |
| - | 3.4% | |
| 9.0 | 9.8 | |
| 7 days ago | 4 days ago | |
| Python | C++ | |
| Apache License 2.0 | GNU Lesser General Public License v3.0 only |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
naja
Posts with mentions or reviews of naja.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-10-11.
-
Naja-Verilog: stand-alone structural (gate-level) parser
Hi everyone, If you need to build C++ (or Python) application loading gate level verilog, similar to the one at the input of FPGA PnR tools, https://github.com/xtofalex/naja-verilog is available. This parser has been designed to allow the construction on the fly of any netlist data structure. One note: if you need also a C++ netlist data structure (with Python bindings) to build netlist analysis or editing tools on top, Naja SNL: https://github.com/xtofalex/naja is also ready for use. Hope this is useful. If it is or if you face any issue, please reach to me. Feedback welcome.
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Show HN: Naja-Verilog – Structural Verilog Parser
The project's other github repo is better to learn more about the project: https://github.com/xtofalex/naja
The linked repo doesn't have a informative Readme. An example showing showing Naja differs from existing tools would help people unfamiliar with Electronic Design Automation, like me.
- Naja - Open-source data structures for EDA back end tools development
- Show HN: Naja – open-source data structures for EDA back end tools development
verilator
Posts with mentions or reviews of verilator.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-10-11.
-
What's new for RISC-V in LLVM 17
You may want to check out Verilator:
https://verilator.org/
- How to run & simulate system verilog files on VScode?
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Choosing a Verification Methodology
relevant issue
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Designing Billions of Circuits with Code
One notable exception is Verilator which is growing fast and competes welll with commercial Verilog simulators (https://github.com/verilator/verilator)
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Error when running cocotb using cocotb-test
It is 4.106, check https://github.com/verilator/verilator/issues/2778 for more details.
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Verilator: Suggestions for verification framework?
Yeah, there is currently a bug and only one specific version of verilator works with cocotb (4.106). Hopefully it will be fixed soon. Go make noise here: https://github.com/verilator/verilator/issues/2778.
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Vitis HLS and Verilator
Okay, made it. Problem is, that my account is flagged as soon as I created it, I am marked as "spammy", and my "comments will only be shown in staff mode". https://github.com/verilator/verilator/issues/3159
- Attention to everyone that is using Verilator and C++! DO NOT update your GCC Package to version 11.1, because it will cause Verilator's object files to fail to compile properly. I have been dealing with this issue for four days straight and have only now found the solution. You have been warned.
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Systemverilog / verilog functional editor not like vivado
If you will help me with systemverilog black box discusion (I have very low systemverilog experience) and verilator will get update then I will upload on github plugin to Sublime Text which lint whole file every time when you stop typing. Currently I have plugin based on Vivado's compiler, but compilation of simple verilog file takes 1'400ms...
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eProcessor is a project that will create a open source RISC-V core for High Performance Computing (HPC)
You have verilator which is a open source simulator , so it is feasible that a "user" could fix a bug or implement a feature (i does not have to be some individual, a business or a university could do it to).
What are some alternatives?
When comparing naja and verilator you can also consider the following projects:
naja-verilog - A standalone structural (gate-level) verilog parser
wavedrom - :ocean: Digital timing diagram rendering engine