Vitis HLS and Verilator

This page summarizes the projects mentioned and recommended in the original post on /r/FPGA
Verilog system-verilog verilog-simulator Verilator Compilers

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  • HLS-Tiny-Tutorials

    This is forked from Xilinx HLS-Tiny-Tutorial. I'm learning HLS and adding Verilator testbench to verify the generated RTL

  • verilator_tb

    Drivers and Checkers to be used with Verilator

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

  • verilator

    Verilator open-source SystemVerilog simulator and lint system

    Okay, made it. Problem is, that my account is flagged as soon as I created it, I am marked as "spammy", and my "comments will only be shown in staff mode". https://github.com/verilator/verilator/issues/3159

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a more popular project.

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