livehd
Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation (by masc-ucsc)
biriscv
32-bit Superscalar RISC-V CPU (by ultraembedded)
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| livehd | biriscv | |
|---|---|---|
| 1 | 6 | |
| 197 | 749 | |
| 1.0% | - | |
| 9.2 | 0.0 | |
| 1 day ago | over 2 years ago | |
| Verilog | Verilog | |
| GNU General Public License v3.0 or later | Apache License 2.0 |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
livehd
Posts with mentions or reviews of livehd.
We have used some of these posts to build our list of alternatives
and similar projects.
biriscv
Posts with mentions or reviews of biriscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-06-21.
What are some alternatives?
When comparing livehd and biriscv you can also consider the following projects:
hdl - HDL libraries and projects
riscv - RISC-V CPU Core (RV32IM)
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
open-register-design-tool - Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
sdspi - SD-Card controller, using either SPI, SDIO, or eMMC interfaces
serv - SERV - The SErial RISC-V CPU
zipcpu - A small, light weight, RISC CPU soft core
cpu11 - Revengineered ancient PDP-11 CPUs, originals and clones
vgasim - A Video display simulator
wbicapetwo - Wishbone to ICAPE interface conversion
RISC-V - Design implementation of the RV32I Core in Verilog HDL with Zicsr extension