hdl_checker
Repurposing existing HDL tools to help writing better code (by suoto)
cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python (by cocotb)
hdl_checker | cocotb | |
---|---|---|
4 | 28 | |
183 | 1,607 | |
- | 2.4% | |
0.0 | 9.7 | |
5 months ago | 4 days ago | |
Python | Python | |
GNU General Public License v3.0 only | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
hdl_checker
Posts with mentions or reviews of hdl_checker.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-02-23.
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Any better options than Sigasi?
I've written a LSP that uses modelsim, ghdl or Vivado to do error checking: https://github.com/suoto/hdl_checker
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What Editor is Everyone Using for FPGA design? (2021)
NeoVim + CoC + hdl_checker
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VHDL native lsp
As others mentioned, rust_hdl and ghdl ls are worth checking out. If your project has both VHDL and Verilog/SystemVerilog, might be worth checking https://github.com/suoto/hdl_checker (disclaimer, I'm the author). It's got less LS features than the other two but if you use it with modelsim it'll provide mixed language syntax check.
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IDE / Editor of choice
Specifically for HDL-files a lot of progress has been made in the last couple of years on lsp-mode and external LSP servers for code analysis of both VHDL and SystemVerilog. For SV I use the https://github.com/suoto/hdl_checker server that passes the code you are working on live to the Linting engine in Questa/ModelSim and marks the warning lines in the editor. It's nice to get immediate feedback on missing semicolons etc. although it still has a hard time handling large projects.
cocotb
Posts with mentions or reviews of cocotb.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-07-04.
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Designing a Low Latency 10G Ethernet Core
The use of cocotb and pyuvm for verification
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How is Python used in test automation in embedded systems?
For FPGA/HDL work, there's cocotb
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Introducing CoHDL
At the moment, it is not possible to directly simulate synthesizable contexts. In principle, I could add a simulator to CoHDL. As a Python implementation, it would be orders of magnitude slower than other solutions. Instead, I am using Cocotb to validate the generated VHDL and for the unit tests in the GitHub repository. There is also some very, very experimental support for formal verification, but it will take some time for that to become usable.
- Use cocotb to test and verify chip designs in Python
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Trying to learn and work with FPGAs
On the topic of simulation, you don't have to restrict yourself to using Verilog or VHDL to write your test benches. For example, Verilator lets you write them in C++, cocotb lets you use Python, and if you use SpinalHDL you will drive the underlying simulator using Scala.
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Help understanding how this makefile works?
I know it might be difficult without much context, but this makefile is called by a top level makefile. very confused if lines 35-74 do anything. They seem to be a mix of real makefile syntax and just straight up comments. what do these lines do?
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COBS protocol decoder progress
Learn more about this here: https://www.cocotb.org/
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AXI-Stream meme
Also consider cocotb, this thread has some compelling arguments. I'd say as a student, learning industry tools isn't necessarily the best thing you could spend your time on. Getting fast at design AND verification, where you can maintain flow state and run better microexperiments means you will understand more, faster.
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cocotb
Have you tried looking at the mixed language example?
- We're trying to sort this out with some of our engineers, so please humor - Do you prefer VHDL or Verilog?
What are some alternatives?
When comparing hdl_checker and cocotb you can also consider the following projects:
completor.vim - Async completion framework made ease.
cocotbext-axi - AXI interface modules for Cocotb
rust_hdl
cocotb-test - Unit testing for cocotb
veridian - A SystemVerilog Language Server
amaranth - A modern hardware definition language and toolchain based on Python
teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
chiselverify - A dynamic verification library for Chisel.
vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
edalize - An abstraction library for interfacing EDA tools
SpinalHDL - Scala based HDL
hdl_checker vs completor.vim
cocotb vs cocotbext-axi
hdl_checker vs rust_hdl
cocotb vs cocotb-test
hdl_checker vs veridian
cocotb vs amaranth
hdl_checker vs teroshdl-documenter-demo
cocotb vs chiselverify
hdl_checker vs vscode-terosHDL
cocotb vs teroshdl-documenter-demo
hdl_checker vs edalize
cocotb vs SpinalHDL