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Over the past few months, I have been working on CoHDL, a hardware description language embedded in Python. Similar to existing solutions like MyHDL, it works by inspecting and translating the abstract syntax tree of Python functions. The initial idea was to explore whether async/await coroutines could be used as an abstraction for state machines.
At the moment, it is not possible to directly simulate synthesizable contexts. In principle, I could add a simulator to CoHDL. As a Python implementation, it would be orders of magnitude slower than other solutions. Instead, I am using Cocotb to validate the generated VHDL and for the unit tests in the GitHub repository. There is also some very, very experimental support for formal verification, but it will take some time for that to become usable.
Nice! Need to check this out, CoHDL seems to have similarities to my work (https://dl.acm.org/doi/abs/10.1145/3549821, https://github.com/tilk/yieldfsm ).