Lion: A formally verified, 5-stage pipeline RISC-V core

• lion

  10 242 4.3 Haskell

  Where Lions Roam: RISC-V on the VELDT (by standardsemiconductor)

  

• cocotb

  28 1,599 9.7 Python

  cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

  

After playing with some of the alternative HDLs (and even trying to make my own at one point) I've come back to just coding the design in VHDL (which I prefer over Verilog/SystemVerilog) and using cocotb (https://github.com/cocotb/cocotb) for creating testbenches. I think in a lot of cases using VHDL generate statements can do a lot of the things these alternative HDLs are trying to do. The alternative HDLs try to shoehorn HDL semantics (everything happens in parallel) into languages that are serial and it ends up being awkward.

Get comfortable with an HDL. Use something like cocotb to generate testbenches.

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