hdl_checker
cocotb-bus
| hdl_checker | cocotb-bus | |
|---|---|---|
| 4 | 1 | |
| 183 | 46 | |
| - | - | |
| 0.0 | 3.7 | |
| 5 months ago | 2 months ago | |
| Python | Python | |
| GNU General Public License v3.0 only | GNU General Public License v3.0 or later |
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hdl_checker
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Any better options than Sigasi?
I've written a LSP that uses modelsim, ghdl or Vivado to do error checking: https://github.com/suoto/hdl_checker
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What Editor is Everyone Using for FPGA design? (2021)
NeoVim + CoC + hdl_checker
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VHDL native lsp
As others mentioned, rust_hdl and ghdl ls are worth checking out. If your project has both VHDL and Verilog/SystemVerilog, might be worth checking https://github.com/suoto/hdl_checker (disclaimer, I'm the author). It's got less LS features than the other two but if you use it with modelsim it'll provide mixed language syntax check.
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IDE / Editor of choice
Specifically for HDL-files a lot of progress has been made in the last couple of years on lsp-mode and external LSP servers for code analysis of both VHDL and SystemVerilog. For SV I use the https://github.com/suoto/hdl_checker server that passes the code you are working on live to the Linting engine in Questa/ModelSim and marks the warning lines in the editor. It's nice to get immediate feedback on missing semicolons etc. although it still has a hard time handling large projects.
cocotb-bus
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Cocotb
The cocotb bus repo has many of the useful drivers and monitors. https://github.com/cocotb/cocotb-bus/tree/master/src/cocotb_bus. There is also https://github.com/alexforencich/cocotbext-axi for some relevant AXI examples that you can also just use.
What are some alternatives?
completor.vim - Async completion framework made ease.
cocotbext-axi - AXI interface modules for Cocotb
rust_hdl
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
veridian - A SystemVerilog Language Server
sphinxcontrib-hdl-diagrams - Sphinx Extension which generates various types of diagrams from Verilog code.
vcdvcd - Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
turbobus - TurboBus is an opinionated implementation of Command Responsibility Segregation pattern in python.
vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development