cocotb-bus VS turbobus

Compare cocotb-bus vs turbobus and see what are their differences.

cocotb-bus

Pre-packaged testbenching tools and reusable bus interfaces for cocotb (by cocotb)

turbobus

TurboBus is an opinionated implementation of Command Responsibility Segregation pattern in python. (by cafadev)
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cocotb-bus turbobus
1 1
46 2
- -
3.7 6.9
2 months ago 23 days ago
Python Python
GNU General Public License v3.0 or later -
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
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cocotb-bus

Posts with mentions or reviews of cocotb-bus. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-11-07.
  • Cocotb
    3 projects | /r/FPGA | 7 Nov 2021
    The cocotb bus repo has many of the useful drivers and monitors. https://github.com/cocotb/cocotb-bus/tree/master/src/cocotb_bus. There is also https://github.com/alexforencich/cocotbext-axi for some relevant AXI examples that you can also just use.

turbobus

Posts with mentions or reviews of turbobus. We have used some of these posts to build our list of alternatives and similar projects.

What are some alternatives?

When comparing cocotb-bus and turbobus you can also consider the following projects:

cocotbext-axi - AXI interface modules for Cocotb

Bus-Departure-Board - A selection of Python programs which will retrieve live bus and rail UK open data and output it to a ER-OLEDM032 (256X64) display screen.

cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

ecs_pattern - ECS pattern (Entity Component System) for creating games on python

sphinxcontrib-hdl-diagrams - Sphinx Extension which generates various types of diagrams from Verilog code.

TextBlob - Simple, Pythonic, text processing--Sentiment analysis, part-of-speech tagging, noun phrase extraction, translation, and more.

hdl_checker - Repurposing existing HDL tools to help writing better code

autoregistry - Automatic registry design-pattern library for mapping names to functionality.

vcdvcd - Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.

eventsourcing - A library for event sourcing in Python.

fusesoc - Package manager and build abstraction tool for FPGA/ASIC development

Mediator.Net - A simple mediator for .Net for sending command, publishing event and request response with pipelines supported