cocotb-bus
Pre-packaged testbenching tools and reusable bus interfaces for cocotb (by cocotb)
cocotbext-axi
AXI interface modules for Cocotb (by alexforencich)
| cocotb-bus | cocotbext-axi | |
|---|---|---|
| 1 | 4 | |
| 46 | 184 | |
| - | - | |
| 3.7 | 4.6 | |
| 2 months ago | 6 months ago | |
| Python | Python | |
| GNU General Public License v3.0 or later | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
cocotb-bus
Posts with mentions or reviews of cocotb-bus.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-11-07.
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Cocotb
The cocotb bus repo has many of the useful drivers and monitors. https://github.com/cocotb/cocotb-bus/tree/master/src/cocotb_bus. There is also https://github.com/alexforencich/cocotbext-axi for some relevant AXI examples that you can also just use.
cocotbext-axi
Posts with mentions or reviews of cocotbext-axi.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-04-04.
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Having trouble with cocotb AXI simulation, cocotb.scheduler error
0.00ns INFO ..b.dma_wrapper.m_axi_s2mm AXI slave model (write) 0.00ns INFO ..b.dma_wrapper.m_axi_s2mm cocotbext-axi version 0.1.24 0.00ns INFO ..b.dma_wrapper.m_axi_s2mm Copyright (c) 2021 Alex Forencich 0.00ns INFO ..b.dma_wrapper.m_axi_s2mm https://github.com/alexforencich/cocotbext-axi 0.00ns DEBUG gpi m_axi_s2mm_awvalid has 1 elements 0.00ns DEBUG gpi m_axi_s2mm_awprot has 3 elements 0.00ns INFO ..b.dma_wrapper.m_axi_s2mm Reset de-asserted 0.00ns DEBUG gpi m_axi_s2mm_wvalid has 1 elements 0.00ns INFO ..b.dma_wrapper.m_axi_s2mm Reset de-asserted 0.00ns DEBUG gpi m_axi_s2mm_bvalid has 1 elements 0.00ns DEBUG gpi m_axi_s2mm_bready has 1 elements 0.00ns DEBUG gpi m_axi_s2mm_bresp has 2 elements 0.00ns INFO ..b.dma_wrapper.m_axi_s2mm Reset de-asserted 0.00ns DEBUG gpi m_axi_s2mm_awaddr has 32 elements
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[CocoTB for beginners]: FPGA/ASIC Testbenches in Python + Automated Testing in GitHub​
I was hoping to decouple the designs from any particular vendor as much as I could so I would interface with the core (dut) with a Cocotb AXI Lite master to get/set registers. Then if I were using something like an AXI Stream to send/receive audio or video data there was a Cocotb python driver to process the data in the test bench. As an example, in part 5 the graphics core generated a 16x4 color bar image over AXI video stream that was captured by a Cocotb AXI Stream sink and then 'displayed' as hex values in one of the test.
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Simulating AXI Accessing to DDR
This is where you can use a BFM (bus functional model). Basically, you can connect your design to a simulation model of the RAM. I wrote some cocotb extensions for doing stuff like this in cocotb, you can give that a try, assuming your code works with a simulator that's compatible with cocotb: https://github.com/alexforencich/cocotbext-axi
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Cocotb
The cocotb bus repo has many of the useful drivers and monitors. https://github.com/cocotb/cocotb-bus/tree/master/src/cocotb_bus. There is also https://github.com/alexforencich/cocotbext-axi for some relevant AXI examples that you can also just use.
What are some alternatives?
When comparing cocotb-bus and cocotbext-axi you can also consider the following projects:
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
sphinxcontrib-hdl-diagrams - Sphinx Extension which generates various types of diagrams from Verilog code.
verilog-ethernet - Verilog Ethernet components for FPGA implementation
hdl_checker - Repurposing existing HDL tools to help writing better code
rohd - The Rapid Open Hardware Development (ROHD) framework is a framework for describing and verifying hardware in the Dart programming language.
vcdvcd - Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.
pyxsi - Python/C/RTL cosimulation with Xilinx's xsim simulator
turbobus - TurboBus is an opinionated implementation of Command Responsibility Segregation pattern in python.
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development