fpu-sp
edalize
| fpu-sp | edalize | |
|---|---|---|
| 3 | 4 | |
| 21 | 593 | |
| - | - | |
| 6.9 | 7.2 | |
| 2 months ago | 10 days ago | |
| VHDL | Python | |
| Apache License 2.0 | BSD 2-clause "Simplified" License |
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fpu-sp
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Intel discontinues Nios II IP
My team has a solution in place already, which was to write all of our floating point code to call macros rather than putting arithmetic in the code. This allowed us to port easily to an RV32IM CPU (a fork of this one) then memory map an FPU onto it, the macros were then changed to atomically access the FPU registers for any floating point arithmetic. In Intel chips we are using the Nios II floating point hardware 2 (which can be instantiated separately), in other vendors we use a combination of operators from the Opencores FPU and this one, depending upon what operators are selected via generics, the maths library will pick up what configuration is used and choose the available operators.
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High level floating point arithmetic in vhdl
Another really nice one that I found recently, uses a fused multiply add unit rather than seperate multiplier and adder. It's available in both mixed precision (double/single) and single precision flavours.
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Got any good reads on floating point math design?
I recently saw an interesting idea in this VHDL repository which combines addition and multiplication in a single fused multiply add unit. Division and square root are combined as well. In my opinion the FMADD block needs some more pipeline stages.
edalize
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Dropping EDA-GUI's 101
Check out FuseSoC: https://github.com/olofk/fusesoc which can handle Vivado builds for you (utilizing edalize: https://github.com/olofk/edalize) along with some nice package management. It can run against multiple tools so you can also get it to build simulations using Verilator or a commercial EDA tool if you have access to them.
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Introduction to FPGAs
Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
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Compiling Code into Silicon
This reminds me very much of edalize[1], which does something very similar.
[1]: https://github.com/olofk/edalize
- Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
What are some alternatives?
cvfpu - Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
fpu - IEEE 754 floating point library in system-verilog and vhdl
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
mrisc32-a1 - A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA
freepdk-45nm - ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
or1200 - OpenRISC 1200 implementation
apio - :seedling: Open source ecosystem for open FPGA boards
Hastlayer-SDK - Turning .NET software into FPGA hardware for faster execution and lower power usage.
icestudio - :snowflake: Visual editor for open FPGA boards
VHDL-Guide - VHDL Guide
rggen - Code generation tool for control and status registers