dvb_fpga
neorv32
| dvb_fpga | neorv32 | |
|---|---|---|
| 2 | 77 | |
| 96 | 1,423 | |
| - | - | |
| 2.2 | 9.9 | |
| about 1 year ago | 7 days ago | |
| VHDL | C | |
| GNU General Public License v3.0 or later | BSD 3-clause "New" or "Revised" License |
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dvb_fpga
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HDL Coder for Software Defined Radio - taught by Mathworks presented by ORI
You can see just one example of open source FPGA design work at https://github.com/OpenResearchInstitute/dvb_fpga
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Adapter to connect LiteFury M.2 to USB on the PC
I'm working on https://github.com/phase4ground/dvb_fpga and was hoping to use this card to test it, most cards have a ton of things I don't really need, this one seemed a nice alternative
neorv32
- An example of how to add the A ISA extension's LR/SC operations into an open-source architecture
- NEORV32 - A tiny, customizable and highly extensible MCU-class 32-bit RISC-V microcontroller-like SoC written in platform-independent VHDL
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Recommendations for RISC-V on FPGA
How about NEORV32?
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SUGGEST AN OPEN SOURCE RISC-V CORE DESIGNED IN VERILOG
GitHub - stnolting/neorv32: 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. this one is good but is written in VHDL though
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RISCV CPU using PL on Pynq Z2 Development Board
NEORV32 is an open source soft core and very well documented. I would recommend you to take a look at it and play around a bit. And it is certainly possible to have a soft core running on only the PL side without PS interference.
- A tiny 1-Wire controller for FPGAs (in VHDL)
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Anyone want to share some embedded projects they have done?
Maybe not a classic (whatever that means...) project, but I am working (together with others) on a RISC-V microcontroller for FPGAs: https://github.com/stnolting/neorv32
What are some alternatives?
pocket-cnn - CNN-to-FPGA-framework for small CNN, written in VHDL and Python
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
openfpga-SNES - SNES for the Analogue Pocket
linux-on-litex-vexriscv - Linux on LiteX-VexRiscv
spi-fpga - SPI master and SPI slave for FPGA written in VHDL
picoMIPS - picoMIPS processor doing affine transformation
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
ghdl - VHDL 2008/93/87 simulator
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
lxp32-cpu - A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
fpga-zynq - Support for Rocket Chip on Zynq FPGAs