dvb_fpga VS vunit

Compare dvb_fpga vs vunit and see what are their differences.

dvb_fpga

RTL implementation of components for DVB-S2 (by OpenResearchInstitute)
dvb-s2 Fpga Vhdl bch-fec ldpc-codes HacktoberFest
Source Code
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vunit

VUnit is a unit testing framework for VHDL/SystemVerilog (by VUnit)
Vhdl Verification systemverilog-hdl unit-testing Fpga Asic testbench universal-verification-methodology verilog-hdl
Source Code
vunit.github.io
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dvb_fpga vunit
2 10
96 682
- 0.9%
2.2 8.2
about 1 year ago 30 days ago
VHDL VHDL
GNU General Public License v3.0 or later GNU General Public License v3.0 or later
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
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dvb_fpga

Posts with mentions or reviews of dvb_fpga. We have used some of these posts to build our list of alternatives and similar projects.

vunit

Posts with mentions or reviews of vunit. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-02-11.
  • Software languages vs HDLs for verification
    3 projects | /r/FPGA | 11 Feb 2023
    My goto tools for verification in VHDL are UVVM and VUnit
  • Libero - Inefficient Simulations
    1 project | /r/FPGA | 29 Jan 2023
    I think the VUnit vivado example (https://github.com/VUnit/vunit/tree/master/examples/vhdl/vivado) may be a good starting point when working with Xilinx IP outside of an IDE.
  • Books About Testing and Verification
    2 projects | /r/FPGA | 25 Jan 2023
    I learned a lot from https://vunit.github.io/ I even became a better VHDL engineer from this fantastic project. It showed me things I did not know VHDL was capable of.
  • A couple of questions for the experts
    2 projects | /r/FPGA | 22 Dec 2022
  • Reference of verification IPs
    7 projects | /r/FPGA | 2 Nov 2022
    Hey! I haven't seen anyone mention Vunit yet. Vunit has a verification components library with Master and Slave components for a decent amount of buses: Axi, Axi stream, Wishbone, Avalon, Uart. The code isn't 100% bullet proof but it is really useful for testing designs.
  • SystemVerilog testbench library
    1 project | /r/FPGA | 14 Sep 2022
    I agree vunit is great but due to circumstances (you can see post above) I need the testbench to be purely SV (and vunit as you said wouldn't help with all of that, only some of it, as you have pointed out). When I refered to vunit I forgot to link the example: https://github.com/VUnit/vunit/tree/master/examples/verilog/uart/src . I referred more to tge fact it is self checking, and the tasks can be reused in ither tbs as well
  • The Vivado 2021.2 is out thread
    1 project | /r/FPGA | 9 Nov 2021
    As for simulation, the last time I used it there were a lot of features not supported. Not sure where this is documented, but I know VUnit can't support it per https://github.com/VUnit/vunit/issues/209 .
  • How do you do automated testing of your HDL?
    1 project | /r/FPGA | 16 Jun 2021
  • VHDL Testbench Library Comparison
    2 projects | /r/FPGA | 8 Apr 2021
    Please consider adding simulator support to this comparison. For example, Vivado's xsim can't be used with VUnit.
  • The simplest way to automate my testbench?
    1 project | /r/FPGA | 21 Jan 2021
    I think these two examples can help you get started. https://github.com/VUnit/vunit/tree/master/examples/vhdl/array_axis_vcs https://github.com/VUnit/vunit/tree/master/examples/vhdl/generate_tests/

What are some alternatives?

When comparing dvb_fpga and vunit you can also consider the following projects:

pocket-cnn - CNN-to-FPGA-framework for small CNN, written in VHDL and Python

spi-fpga - SPI master and SPI slave for FPGA written in VHDL

openfpga-SNES - SNES for the Analogue Pocket

AXI4 - AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

ghdl - VHDL 2008/93/87 simulator

neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0

catapult-v3-smartnic-re - Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)

OsvvmLibraries - Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.

fpga_puf - :key: Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

dvb_fpga vs pocket-cnn vunit vs spi-fpga dvb_fpga vs openfpga-SNES vunit vs AXI4 dvb_fpga vs spi-fpga vunit vs ghdl dvb_fpga vs neorv32 vunit vs upduino-projects dvb_fpga vs ghdl vunit vs catapult-v3-smartnic-re vunit vs OsvvmLibraries vunit vs fpga_puf