deepsocflow
libsv
deepsocflow | libsv | |
---|---|---|
1 | 2 | |
36 | 19 | |
- | - | |
9.1 | 3.6 | |
7 days ago | over 2 years ago | |
Python | SystemVerilog | |
Apache License 2.0 | MIT License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
deepsocflow
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Xilinx xsim is BLAZINGLY FAST. Xsim dumping all signals 5x faster than Icarus Verilog dumping no signals!
Here's the testbench. I've written a python script to generate test vectors, generate batch file for xsim, run icarus/xsim and compare output. Feel free to star my project repo, if you like it.
libsv
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Skid Buffer
https://github.com/bensampson5/libsv/blob/main/libsv/fifos/skid_buffer.svhttps://libsv.readthedocs.io/en/latest/skid_buffer.html
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What should a modern IP library look like?
If you're interested in checking that out here's the link to the GitHub page for LibSV: https://github.com/bensampson5/libsv.
What are some alternatives?
FPGA-Video-Processing - Realtime video processing w/ Gaussian + Sobel Filters targeting Artix-7 FPGA
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
DFHDL - DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
cheshire - A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
ulm-on-ice - ULM (Ulm Lecture Machine) on ice40
opentitan - OpenTitan: Open source silicon root of trust
basys3_fpga_sandbox - Learning the basics of Systemverilog, testbench and more.
eurorack-pmod - A eurorack-friendly audio frontend compatible with many FPGA boards.
VHDL_Lib - Library of VHDL components that are useful in larger designs.