libsv VS ulm-on-ice

Compare libsv vs ulm-on-ice and see what are their differences.

libsv

An open source, parameterized SystemVerilog digital hardware IP library (by bensampson5)
Verilog Systemverilog Hdl IP Fpga Asic digital-design asic-library fpga-library Hardware hardware-libraries hardware-designs
Source Code
libsv.readthedocs.io
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ulm-on-ice

ULM (Ulm Lecture Machine) on ice40 (by michael-lehn)
Fpga Verilog
Source Code
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libsv ulm-on-ice
2 1
19 2
- -
3.6 5.6
about 2 years ago about 1 year ago
SystemVerilog SystemVerilog
MIT License GNU General Public License v3.0 only
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
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libsv

Posts with mentions or reviews of libsv. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-11-06.
  • Skid Buffer
    1 project | /r/FPGA | 23 Jul 2022
    https://github.com/bensampson5/libsv/blob/main/libsv/fifos/skid_buffer.svhttps://libsv.readthedocs.io/en/latest/skid_buffer.html
  • What should a modern IP library look like?
    7 projects | /r/FPGA | 6 Nov 2021
    If you're interested in checking that out here's the link to the GitHub page for LibSV: https://github.com/bensampson5/libsv.

ulm-on-ice

Posts with mentions or reviews of ulm-on-ice. We have used some of these posts to build our list of alternatives and similar projects.
  • Building your own computer with an FPGA
    1 project | /r/FPGA | 22 Oct 2023
    I used a Lattice ice40 FPGA (e.g. icebreaker) FPGA to implement a simple RISC microprocessor. For the hardware description I used SystemVerilog and an open source toolchain. The source code is on GitHub.

What are some alternatives?

When comparing libsv and ulm-on-ice you can also consider the following projects:

fusesoc - Package manager and build abstraction tool for FPGA/ASIC development

FPGA-Video-Processing - Realtime video processing w/ Gaussian + Sobel Filters targeting Artix-7 FPGA

DFHDL - DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language

BrianHG-DDR3-Controller - DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

riscv-simple-sv - A simple RISC V core for teaching

cheshire - A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

VeriGPU - OpenSource GPU, in Verilog, loosely based on RISC-V ISA

scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog

opentitan - OpenTitan: Open source silicon root of trust

basys3_fpga_sandbox - Learning the basics of Systemverilog, testbench and more.

libsv vs fusesoc ulm-on-ice vs FPGA-Video-Processing libsv vs DFHDL ulm-on-ice vs BrianHG-DDR3-Controller libsv vs ibex ulm-on-ice vs riscv-simple-sv libsv vs cheshire ulm-on-ice vs VeriGPU libsv vs FPGA-Video-Processing ulm-on-ice vs scr1 libsv vs opentitan libsv vs basys3_fpga_sandbox