ulm-on-ice
scr1
| ulm-on-ice | scr1 | |
|---|---|---|
| 1 | 2 | |
| 2 | 783 | |
| - | 2.3% | |
| 5.6 | 3.0 | |
| about 1 year ago | 7 days ago | |
| SystemVerilog | SystemVerilog | |
| GNU General Public License v3.0 only | GNU General Public License v3.0 or later |
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ulm-on-ice
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Building your own computer with an FPGA
I used a Lattice ice40 FPGA (e.g. icebreaker) FPGA to implement a simple RISC microprocessor. For the hardware description I used SystemVerilog and an open source toolchain. The source code is on GitHub.
scr1
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Looking for a suitable open-source RISC-V for an embedded project
Would this be suitable? https://github.com/syntacore/scr1 I haven't used it, but I saw it in Riscduino project which continues to appear in Open MPWs.
- Mikron MIK32 – Made in Russia 32-bit RISC-V MCU... for about $6
What are some alternatives?
FPGA-Video-Processing - Realtime video processing w/ Gaussian + Sobel Filters targeting Artix-7 FPGA
riscv-simple-sv - A simple RISC V core for teaching
libsv - An open source, parameterized SystemVerilog digital hardware IP library
BrianHG-DDR3-Controller - DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
friscv - RISCV CPU implementation in SystemVerilog
Cores-VeeR-EL2 - VeeR EL2 Core
VeriGPU - OpenSource GPU, in Verilog, loosely based on RISC-V ISA
clic - RISC-V fast interrupt controller
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.