ulm-on-ice
riscv-simple-sv
| ulm-on-ice | riscv-simple-sv | |
|---|---|---|
| 1 | 2 | |
| 2 | 145 | |
| - | - | |
| 5.6 | 0.0 | |
| about 1 year ago | over 2 years ago | |
| SystemVerilog | SystemVerilog | |
| GNU General Public License v3.0 only | BSD 3-clause "New" or "Revised" License |
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ulm-on-ice
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Building your own computer with an FPGA
I used a Lattice ice40 FPGA (e.g. icebreaker) FPGA to implement a simple RISC microprocessor. For the hardware description I used SystemVerilog and an open source toolchain. The source code is on GitHub.
riscv-simple-sv
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Simple CPU cores to study?
I published the code on GitHub: https://github.com/tilk/riscv-simple-sv
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Need help in CPU design
I need to run a RISC-V softcore in my FPGA. I don't need to develop the core myself, which means I can use one with good support and that is well implemented (if someone knows a good one, tell me in the comments, please). Since I'm a little new to this area I started by using a simple core: https://github.com/tilk/riscv-simple-sv, however, I'm a little lost in the steps that I need to do. First, I need to put the core in my FPGA. Then, how can I execute code in the core? Do I need to put the machine code into the ROM? And how can I do that? What if I want to debug my C programs that are supposed to run on the core?
What are some alternatives?
FPGA-Video-Processing - Realtime video processing w/ Gaussian + Sobel Filters targeting Artix-7 FPGA
cv32e40p - CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
libsv - An open source, parameterized SystemVerilog digital hardware IP library
scr1 - SCR1 is a high-quality open-source RISC-V MCU core in Verilog
BrianHG-DDR3-Controller - DDR3 Controller v1.60, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
gdb-stub - gdb-proxy implementation for bonfire
VeriGPU - OpenSource GPU, in Verilog, loosely based on RISC-V ISA
picoMIPS - picoMIPS processor doing affine transformation
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
rhd - Tiny 16-bit RISC Core