OpenFPGA
An Open-source FPGA IP Generator (by lnis-uofu)
darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night! (by darklife)
OpenFPGA | darkriscv | |
---|---|---|
3 | 3 | |
744 | 1,897 | |
2.2% | 2.0% | |
9.7 | 6.3 | |
6 days ago | 18 days ago | |
Verilog | Verilog | |
MIT License | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
OpenFPGA
Posts with mentions or reviews of OpenFPGA.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-02-12.
- OpenFPGA. The future of video game preservation
-
Clear – The Open Source FPGA ASIC
Looks like this has been put together by Efabless themselves. I dont think the rtl would be too different from OpenFPGA(https://github.com/lnis-uofu/OpenFPGA) married to the caravel f/w.
darkriscv
Posts with mentions or reviews of darkriscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-08-20.
-
As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?
This guy here has designed his 2 stage RISC-V in just one right: https://github.com/darklife/darkriscv.
- Are there any dual-GBE, PoE-capable SBCs?
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Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.