xfcp
litex
xfcp | litex | |
---|---|---|
5 | 29 | |
51 | 2,683 | |
- | - | |
0.0 | 9.7 | |
about 1 year ago | 6 days ago | |
Verilog | C | |
MIT License | GNU General Public License v3.0 or later |
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xfcp
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Ethernet PC-FPGA interface
This is exactly what I created https://github.com/alexforencich/xfcp for - Ethernet and serial to multiple internal components, with the ability to enumerate said components.
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Options for control and configuration of FPGA from PC
This is basically what I made XFCP for: https://github.com/alexforencich/xfcp
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Share some github FPGA projects (bonus if they include C++, Python, or other files)
Simple interface framework for connecting Python to FPGA designs over a serial port or over Ethernet: https://github.com/alexforencich/xfcp .
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FPGA development live stream: FPGA board bring-up and testing of high-speed serializers
I'll use my XFCP project to interface with the FPGA from Python via a USB serial chip. This provides access to the I2C bus on the board, for configuring the PLL chips and interfacing with the QSFP28 optical transceivers. Additionally, it connects to the dynamic reconfiguration ports (DRP) on the GTY transceivers, and I'll use that for performing BER measurements at 25 Gbps through a handful of QSFP28 cables and optical modules. It looks like I might also have to do some fine-tuning of some of the analog parameters on the transceivers (namely pre-emphasis).
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FPGA development live stream: FPGA board bring-up and testing
I recently acquired a pair of rather large FPGA boards that have a bunch of high-speed IO. I figure it might be interesting to show the process for bringing them up in terms of the reference clock generation and distribution components on the board for the high-speed serializers, as well as performing some simple sanity checks (BER testing) on all of the interfaces to make sure everything is operational. I'll use my XFCP project to interface with the FPGA from Python for configuring the clocking components over I2C and for performing the BER measurements on the GTY transceivers via DRP.
litex
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FPGA Dev Boards for $150 or Less
https://github.com/enjoy-digital/litex
they have tutorials, you can get compatible boards for around $20
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Need help to build a RISC-V Processor on Artix-7 FPGA: Final Year Engineering Project Guide
With LiteX you can synthesize a VexRiscV processor. You can run Linux on it. The toolchain is pretty easy to use, as long as you use Xilinx Vivado to compile to gateware.
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Sunset TCL scripts ?
LiteX is a great example of a Python-first flow. However, they have chosen not to subordinate the scripting environment to a GUI toolchain - EDA vendors are unlikely to choose the same trade.
- synthesizing and using the Ibex RISC-V core
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Been messing around with litex and migen on my Tang Primer 20K
To lean these: https://github.com/enjoy-digital/litex, https://github.com/m-labs/migen
- CPU design for college project
- How can I learn about RISC-V and use case? I want to do a project for begginers
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How Much Would It Cost For A Truly Open Source RISC-V SOC?
If you use LiteX to generate a VexRiscV system-on-a-chip, you can include an open source DDR DRAM PHY. This works on Xilinx Spartan-6, Spartan7Artix7/Kintex7/Virtex7 FPGAs, and Lattice ECP5 FPGAs. DDR/LPDDR/DDR2/DDR3 depending on the FPGA.
- LiteX: Build Hardware Easily
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Using FPGAs for computations as a beginner
I am interested in trying out FPGAs for the purpose of running specific calculations more efficiently. Since the calculations themselves are quite complex, I would need to be able to program in a relatively high-level language. I've seen that designing SoC in Python is possible, for example with Litex (https://github.com/enjoy-digital/litex) or Amaranth (https://github.com/amaranth-lang/). I don't want to spend hundreds of hours learning about FPGAs, but I'm prepared to take on a challenge.
What are some alternatives?
SBusFPGA - Stuff to put a FPGA in a SBus system (SPARCstation)
nmigen-tutorial - A tutorial for using nmigen
verilog-ethernet - Verilog Ethernet components for FPGA implementation
SpinalHDL - Scala based HDL
corundum - Open source FPGA-based NIC and platform for in-network compute
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
SaxonSoc - SoC based on VexRiscv and ICE40 UP5K
satcat5 - SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
openwifi - open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
FPGA_RealTime_and_Static_Sobel_Edge_Detection - Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images