xfcp
satcat5
xfcp | satcat5 | |
---|---|---|
5 | 25 | |
51 | 390 | |
- | 9.8% | |
0.0 | 3.8 | |
about 1 year ago | 2 months ago | |
Verilog | VHDL | |
MIT License | CERN Open Hardware Licence Version 2 - Weakly Reciprocal |
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xfcp
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Ethernet PC-FPGA interface
This is exactly what I created https://github.com/alexforencich/xfcp for - Ethernet and serial to multiple internal components, with the ability to enumerate said components.
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Options for control and configuration of FPGA from PC
This is basically what I made XFCP for: https://github.com/alexforencich/xfcp
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Share some github FPGA projects (bonus if they include C++, Python, or other files)
Simple interface framework for connecting Python to FPGA designs over a serial port or over Ethernet: https://github.com/alexforencich/xfcp .
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FPGA development live stream: FPGA board bring-up and testing of high-speed serializers
I'll use my XFCP project to interface with the FPGA from Python via a USB serial chip. This provides access to the I2C bus on the board, for configuring the PLL chips and interfacing with the QSFP28 optical transceivers. Additionally, it connects to the dynamic reconfiguration ports (DRP) on the GTY transceivers, and I'll use that for performing BER measurements at 25 Gbps through a handful of QSFP28 cables and optical modules. It looks like I might also have to do some fine-tuning of some of the analog parameters on the transceivers (namely pre-emphasis).
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FPGA development live stream: FPGA board bring-up and testing
I recently acquired a pair of rather large FPGA boards that have a bunch of high-speed IO. I figure it might be interesting to show the process for bringing them up in terms of the reference clock generation and distribution components on the board for the high-speed serializers, as well as performing some simple sanity checks (BER testing) on all of the interfaces to make sure everything is operational. I'll use my XFCP project to interface with the FPGA from Python for configuring the clocking components over I2C and for performing the BER measurements on the GTY transceivers via DRP.
satcat5
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Layout of Rust's u128 and i128 changed
I needed 128-bit and 256-bit integers on an embedded project recently.
In short, it was for fixed-point digital signal processing. The raw input and output samples were int64_t. We needed to add, subtract, multiply, and accumulate these to do filtering and linear regression with no loss of precision.
Conventional bigintegers weren't an option because the target application doesn't allow heap allocation. So we rolled our own [1] stack-allocated, fixed-width big integer class.
[1] https://github.com/the-aerospace-corporation/satcat5/blob/ma...
- Show HN: SatCat5, the open-source FPGA Ethernet switch
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CRC32 algorithm match value between 96 bit wide data bus and 24 bit wide data bus
And here's an open-source implementation I wrote a few years back. You can skip the part at the end that handles variable-length trailing bytes, since you have a fixed-width input.
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Questions about lattice ecp5 fpga.
My SatCat5 project also has a few options. Anything under src/vhdl/common/cfgbus_* can be connected to AXI or Wishbone with a simple adapter.
- SatCat5: FPGA gateware that implements a low-power, mixed-media Ethernet switch
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GPSDO without VCXO?
For an all-digital solution, here's an NCO that generates an arbitrary-frequency square wave from a numeric counter.
- network switch
What are some alternatives?
SBusFPGA - Stuff to put a FPGA in a SBus system (SPARCstation)
verilog-ethernet - Verilog Ethernet components for FPGA implementation
litex - Build your hardware, easily!
SpinalHDL - Scala based HDL
surf - A huge VHDL library for FPGA development
corundum - Open source FPGA-based NIC and platform for in-network compute
opentitan - OpenTitan: Open source silicon root of trust
FPGA_RealTime_and_Static_Sobel_Edge_Detection - Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images
chisel - Chisel: A Modern Hardware Design Language