vunit VS hVHDL_example_project

Compare vunit vs hVHDL_example_project and see what are their differences.

vunit

VUnit is a unit testing framework for VHDL/SystemVerilog (by VUnit)
Vhdl Verification systemverilog-hdl unit-testing Fpga Asic testbench universal-verification-methodology verilog-hdl
Source Code
vunit.github.io
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hVHDL_example_project

An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has build scripts for most common FPGAs (by hVHDL)
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vunit hVHDL_example_project
10 10
684 20
1.2% -
8.2 8.9
about 1 month ago about 2 months ago
VHDL VHDL
GNU General Public License v3.0 or later MIT License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

vunit

Posts with mentions or reviews of vunit. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-02-11.
  • Software languages vs HDLs for verification
    3 projects | /r/FPGA | 11 Feb 2023
    My goto tools for verification in VHDL are UVVM and VUnit
  • Libero - Inefficient Simulations
    1 project | /r/FPGA | 29 Jan 2023
    I think the VUnit vivado example (https://github.com/VUnit/vunit/tree/master/examples/vhdl/vivado) may be a good starting point when working with Xilinx IP outside of an IDE.
  • Books About Testing and Verification
    2 projects | /r/FPGA | 25 Jan 2023
    I learned a lot from https://vunit.github.io/ I even became a better VHDL engineer from this fantastic project. It showed me things I did not know VHDL was capable of.
  • A couple of questions for the experts
    2 projects | /r/FPGA | 22 Dec 2022
  • Reference of verification IPs
    7 projects | /r/FPGA | 2 Nov 2022
    Hey! I haven't seen anyone mention Vunit yet. Vunit has a verification components library with Master and Slave components for a decent amount of buses: Axi, Axi stream, Wishbone, Avalon, Uart. The code isn't 100% bullet proof but it is really useful for testing designs.
  • SystemVerilog testbench library
    1 project | /r/FPGA | 14 Sep 2022
    I agree vunit is great but due to circumstances (you can see post above) I need the testbench to be purely SV (and vunit as you said wouldn't help with all of that, only some of it, as you have pointed out). When I refered to vunit I forgot to link the example: https://github.com/VUnit/vunit/tree/master/examples/verilog/uart/src . I referred more to tge fact it is self checking, and the tasks can be reused in ither tbs as well
  • The Vivado 2021.2 is out thread
    1 project | /r/FPGA | 9 Nov 2021
    As for simulation, the last time I used it there were a lot of features not supported. Not sure where this is documented, but I know VUnit can't support it per https://github.com/VUnit/vunit/issues/209 .
  • How do you do automated testing of your HDL?
    1 project | /r/FPGA | 16 Jun 2021
  • VHDL Testbench Library Comparison
    2 projects | /r/FPGA | 8 Apr 2021
    Please consider adding simulator support to this comparison. For example, Vivado's xsim can't be used with VUnit.
  • The simplest way to automate my testbench?
    1 project | /r/FPGA | 21 Jan 2021
    I think these two examples can help you get started. https://github.com/VUnit/vunit/tree/master/examples/vhdl/array_axis_vcs https://github.com/VUnit/vunit/tree/master/examples/vhdl/generate_tests/

hVHDL_example_project

Posts with mentions or reviews of hVHDL_example_project. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-01-27.

What are some alternatives?

When comparing vunit and hVHDL_example_project you can also consider the following projects:

spi-fpga - SPI master and SPI slave for FPGA written in VHDL

pymtl3 - Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

AXI4 - AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

hVHDL_floating_point - high level VHDL floating point library for synthesis in fpga

ghdl - VHDL 2008/93/87 simulator

migen - A Python toolbox for building complex digital hardware

upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0

magma - magma circuits

catapult-v3-smartnic-re - Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)

PipelineC - A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

OsvvmLibraries - Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.

litex - Build your hardware, easily!

vunit vs spi-fpga hVHDL_example_project vs pymtl3 vunit vs AXI4 hVHDL_example_project vs hVHDL_floating_point vunit vs ghdl hVHDL_example_project vs migen vunit vs upduino-projects hVHDL_example_project vs magma vunit vs catapult-v3-smartnic-re hVHDL_example_project vs PipelineC vunit vs OsvvmLibraries hVHDL_example_project vs litex