fpu VS edalize

Compare fpu vs edalize and see what are their differences.

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fpu edalize
1 4
46 593
- -
6.1 7.2
2 months ago 11 days ago
VHDL Python
Apache License 2.0 BSD 2-clause "Simplified" License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
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Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

fpu

Posts with mentions or reviews of fpu. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-08-08.
  • High level floating point arithmetic in vhdl
    3 projects | /r/FPGA | 8 Aug 2022
    Another really nice one that I found recently, uses a fused multiply add unit rather than seperate multiplier and adder. It's available in both mixed precision (double/single) and single precision flavours.

edalize

Posts with mentions or reviews of edalize. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2023-02-06.
  • Dropping EDA-GUI's 101
    1 project | /r/FPGA | 17 Feb 2023
    Check out FuseSoC: https://github.com/olofk/fusesoc which can handle Vivado builds for you (utilizing edalize: https://github.com/olofk/edalize) along with some nice package management. It can run against multiple tools so you can also get it to build simulations using Verilator or a commercial EDA tool if you have access to them.
  • Introduction to FPGAs
    9 projects | news.ycombinator.com | 6 Feb 2023
    Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
  • Compiling Code into Silicon
    10 projects | news.ycombinator.com | 7 Dec 2021
    This reminds me very much of edalize[1], which does something very similar.

    [1]: https://github.com/olofk/edalize

  • Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
    3 projects | /r/RISCV | 24 Sep 2021

What are some alternatives?

When comparing fpu and edalize you can also consider the following projects:

neorv32-setups - 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

fusesoc - Package manager and build abstraction tool for FPGA/ASIC development

fpu-sp - IEEE 754 floating point library in system-verilog and vhdl

skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

uart-for-fpga - Simple UART controller for FPGA written in VHDL

freepdk-45nm - ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen

or1200 - OpenRISC 1200 implementation

apio - :seedling: Open source ecosystem for open FPGA boards

spi-fpga - SPI master and SPI slave for FPGA written in VHDL

icestudio - :snowflake: Visual editor for open FPGA boards

Hastlayer-SDK - Turning .NET software into FPGA hardware for faster execution and lower power usage.

rggen - Code generation tool for control and status registers