riscv-boom
neorv32-setups
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| riscv-boom | neorv32-setups | |
|---|---|---|
| 12 | 5 | |
| 1,593 | 52 | |
| 3.0% | - | |
| 7.2 | 8.6 | |
| about 1 month ago | 6 days ago | |
| Scala | VHDL | |
| BSD 3-clause "New" or "Revised" License | BSD 3-clause "New" or "Revised" License |
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riscv-boom
- Is RISC-V ready for HPC? Evaluating the 64-core Sophon SG2042 RISC-V CPU
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Cascade: CPU Fuzzing via Intricate Program Generation
Looks like from Appendix D that only 2 bugs were found in BOOM:
> 1. Inaccurate instruction count when minstret is written by software
I don't know what that means, but having minstret written by software was definitely not something I ever tested. In general, perf counters are likely to be undertested.
> 2. Static rounding is ignored for fdiv.s and fsqrt.s
A mistake was made in only listening to the dynamic rounding mode for the fdiv/sqrt unit. This is one of those bugs that is trivially found if you test for it, but it turns out that no benchmarking ever cared about this and from all of the fuzzers I used when I worked on BOOM, NONE of them hit it (including commercial ones...). Ooops.
Fixed here: https://github.com/riscv-boom/riscv-boom/pull/629/files
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In your opinion, what is the most advanced open source softcore processor?
The two most micro architecturally advanced cores that I know of are BOOM, an out of order RV64GC core with all the features you expect plus sort of weird fancy things like short forward branch predication, and VROOM, another out of order RV64GC core with things like uop fusion and a trace cache.
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PyXHDL - Python Frontend For VHDL And Verilog
it is used in the Berkley Out-of-Order RISC-V processor: https://github.com/riscv-boom/riscv-boom
- Semidynamics Unveils First Customizable RISC-V Cores for End Users
- TechTechPotato (Dr Ian Cutress): "Building High-Performance RISC-V Cores for Everything"
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Open-source RISC-V CPU projects for contribution
SonicBOOM: https://github.com/riscv-boom/riscv-boom
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The Surprising Subtleties of Zeroing a Register
Some cores are open source and you can see for yourself.
Rename logic from BOOM, a RISC-V core written in a DSL embedded in Scala:
https://github.com/riscv-boom/riscv-boom/blob/1ef2bc6f6c98e5...
From RSD, a core designed for FPGAs written in SystemVerilog:
https://github.com/rsd-devel/rsd/blob/master/Processor/Src/R...
And then there's the recently open-sourced XuanTie C910, which contains this Verilog… which is completely unreadable. Seems like it was produced by some kind of code generator that they didn't open-source?
https://github.com/T-head-Semi/openc910/blob/d4a3b947ec9bb8f...
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Anandtech: "IBM Power10 Coming To Market: E1080 for 'Frictionless Hybrid Cloud Experiences'"
We don't have Sifive's specifically but we do have the open source cores they've historically used to design their cores: https://github.com/riscv-boom/riscv-boom https://github.com/chipsalliance/rocket-chip
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Fence instruction implementation in BOOM
If you look at the decoder (https://github.com/riscv-boom/riscv-boom/blob/master/src/main/scala/exu/decode.scala), you can see that the fence instructions are also marked as "unique" instructions. Only one "unique" instruction is allowed in the pipeline at a time.
neorv32-setups
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How to find the pin mapping for connecting Zybo Z7-20 or Nexyx A7 board to a computer over USB-JTAG?
Hello. In my project, I am trying to run NEORV32 processor in an FPGA. My plan is to perform debugging of the design over JTAG after running it on an FPGA. I currently have a Zybo Z7-20 and a Nexyx A7 board at hand. As per my understanding, for both of the boards, I need to find the board pins associated with JTAG and manually connect them through the constraint file. I was going through the reference manuals for both FPGAs but couldn't find the pins that need to be connected.
- RISC-V with AXI Peripheral
- Open-source RISC-V CPU projects for contribution
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A tiny and open-source (BSD) RISC-V SoC for (all!) FPGAs
and by "all" you of course mean some small Cyclones, Lattice ICE40s and Artix7 (see here)
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Risc-v rv32i softcore processor for Zybo-z7-10
There are some example setups here: https://github.com/stnolting/neorv32-setups
What are some alternatives?
rocket-chip - Rocket Chip Generator
picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU
openc910 - OpenXuantie - OpenC910 Core
litex - Build your hardware, easily!
XiangShan - Open-source high-performance RISC-V processor
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
rsd - RSD: RISC-V Out-of-Order Superscalar Processor
fpu - IEEE 754 floating point library in system-verilog and vhdl
riscv-mini - Simple RISC-V 3-stage Pipeline in Chisel
neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
Cores-VeeR-EL2 - VeeR EL2 Core
vivado-risc-v - Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro