riscv-cores-list
neorv32
riscv-cores-list | neorv32 | |
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5 | 77 | |
474 | 1,433 | |
- | - | |
6.0 | 9.9 | |
about 3 years ago | 6 days ago | |
C | ||
- | BSD 3-clause "New" or "Revised" License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-cores-list
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Navi 23 Die (Dimgrey Cavefish) - 237 mm², 11.06BT, TSMC 7nm, 32 CUs, 32 MB IC, 128-bit, PCIe 4.0
For example, the fastest open source RISC-V designs are written with SpinaldHDL or Chisel, rather than a lesser abstracted language like VHDL or (System)Verilog.
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SiFive 21G1 Webinar...
I note that https://github.com/riscv/riscv-cores-list is now archived, and https://riscv.org/risc-v-cores/ is now 404'd...
- Hey guys, I would like to start some project using a RISC-V core. I already extended a RISC-V core by an AXI-based security accelerator. Now I am looking for something new... Do you have some ideas?
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Pine64 unveils RK3566-powered SBC and reveals an upcoming RISC-V board
Is it open source? i read articles saying it will be open source but here (the risc-v foundation wiki) it appears under a commercial license, i also don't see it on the alibaba github.
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Ayuda!
Posting in English would help. Also stating what your purpose is in general helps, otherwise you get generic answers like download one here and burn it into a fpga.
neorv32
- An example of how to add the A ISA extension's LR/SC operations into an open-source architecture
- NEORV32 - A tiny, customizable and highly extensible MCU-class 32-bit RISC-V microcontroller-like SoC written in platform-independent VHDL
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Recommendations for RISC-V on FPGA
How about NEORV32?
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SUGGEST AN OPEN SOURCE RISC-V CORE DESIGNED IN VERILOG
GitHub - stnolting/neorv32: 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. this one is good but is written in VHDL though
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RISCV CPU using PL on Pynq Z2 Development Board
NEORV32 is an open source soft core and very well documented. I would recommend you to take a look at it and play around a bit. And it is certainly possible to have a soft core running on only the PL side without PS interference.
- A tiny 1-Wire controller for FPGAs (in VHDL)
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Anyone want to share some embedded projects they have done?
Maybe not a classic (whatever that means...) project, but I am working (together with others) on a RISC-V microcontroller for FPGAs: https://github.com/stnolting/neorv32
What are some alternatives?
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
linux-on-litex-vexriscv - Linux on LiteX-VexRiscv
OpenLANE-Sky130-Physical-Design-Workshop - Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
picoMIPS - picoMIPS processor doing affine transformation
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
lxp32-cpu - A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
fpga-zynq - Support for Rocket Chip on Zynq FPGAs
serv - SERV - The SErial RISC-V CPU
linux-on-litex-rocket - Run 64-bit Linux on LiteX + RocketChip