rggen
open-register-design-tool
| rggen | open-register-design-tool | |
|---|---|---|
| 3 | 2 | |
| 279 | 182 | |
| 1.8% | 1.6% | |
| 7.7 | 5.3 | |
| 3 months ago | 9 months ago | |
| Ruby | Verilog | |
| MIT License | Apache License 2.0 |
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rggen
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RgGen v0.28.0
I've released RgGen v0.28.0! https://github.com/rggen/rggen/releases/tag/v0.28.0 This release includes following updates.
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RgGen update (support C header file generation)
RgGen is a code generation tool for configuration and status registers. RgGen can generate SV/Verilog/VHDL RTL, UVM RAL model and Markdown documents from readable register map specifications. https://github.com/rggen/rggen
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RgGen update
I just released the latest RgGen v0.26.0! https://github.com/rggen/rggen/releases/tag/v0.26.0
open-register-design-tool
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Thoughts about SystemRDL ?
I have used this compiler (https://github.com/Juniper/open-register-design-tool/wiki/Running-Ordt) to generate a Python model to access registers (I use Python on embedded Linux to read/write registers over SPI to the device).
- Auto Generate Header Files
What are some alternatives?
PeakRDL-uvm - Generate UVM register model from compiled SystemRDL input
livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
PeakRDL-ipxact - Import and export IP-XACT XML register models
gf180mcu-pdk - PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
edalize - An abstraction library for interfacing EDA tools
PeakRDL-html - Generate address space documentation HTML from compiled SystemRDL input
vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
OpenTimer - A High-performance Timing Analysis Tool for VLSI Systems
rggen-sv-rtl - Common SystemVerilog RTL modules for RgGen
biriscv - 32-bit Superscalar RISC-V CPU
hdlConvertor - Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.