rapcores
Robotic Application Processor (by RAPcores)
darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night! (by darklife)
| rapcores | darkriscv | |
|---|---|---|
| 3 | 3 | |
| 22 | 1,892 | |
| - | 1.7% | |
| 0.0 | 6.3 | |
| over 2 years ago | 13 days ago | |
| Verilog | Verilog | |
| ISC License | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
rapcores
Posts with mentions or reviews of rapcores.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-07-21.
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FPGA development automation practices
Our project is: https://github.com/RAPcores/rapcores I have a draft article about the tools we use, but it is several months old now. We are about one year into the project, and I am amazed how every month some new tooling seems to pop up that solves some problem.
- PWM for BLDC motor RPM control on Arty A7 100T
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Lessons learned while building an ASIC design
Really good write up. We recently did a tape out as well and had similar learnings :) Would have definitely been nice to see this a few months ago. As part of our CI we have started parsing with Yosys, Verilator, and IVerilog. I cannot recommend this enough. There is a perfectly capable subset of verilog dialect amongst all three, and gives you nice protability amongst FOSS toolchains. Running parsing checks is a great way to lint/sanity check things. We also put together a simple script to check register initializations that has been really helpful also: https://github.com/RAPcores/rapcores/blob/main/etc/reginit.sh
darkriscv
Posts with mentions or reviews of darkriscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-08-20.
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As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?
This guy here has designed his 2 stage RISC-V in just one right: https://github.com/darklife/darkriscv.
- Are there any dual-GBE, PoE-capable SBCs?
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Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.