neorv32
vivado-risc-v
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neorv32 | vivado-risc-v | |
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77 | 6 | |
1,423 | 738 | |
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9.9 | 7.5 | |
5 days ago | 10 days ago | |
C | Tcl | |
BSD 3-clause "New" or "Revised" License | - |
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neorv32
- An example of how to add the A ISA extension's LR/SC operations into an open-source architecture
- NEORV32 - A tiny, customizable and highly extensible MCU-class 32-bit RISC-V microcontroller-like SoC written in platform-independent VHDL
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Recommendations for RISC-V on FPGA
How about NEORV32?
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SUGGEST AN OPEN SOURCE RISC-V CORE DESIGNED IN VERILOG
GitHub - stnolting/neorv32: 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. this one is good but is written in VHDL though
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RISCV CPU using PL on Pynq Z2 Development Board
NEORV32 is an open source soft core and very well documented. I would recommend you to take a look at it and play around a bit. And it is certainly possible to have a soft core running on only the PL side without PS interference.
- A tiny 1-Wire controller for FPGAs (in VHDL)
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Anyone want to share some embedded projects they have done?
Maybe not a classic (whatever that means...) project, but I am working (together with others) on a RISC-V microcontroller for FPGAs: https://github.com/stnolting/neorv32
vivado-risc-v
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Recommendations for RISC-V on FPGA
Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?
- How can I learn about RISC-V and use case? I want to do a project for begginers
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Open-source RISC-V CPU projects for contribution
For Xilinx FPGAs : https://github.com/eugene-tarassov/vivado-risc-v
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can one run one a linux distro like debian on an fpga?
I know it would run slowly, im not interested in performance, just curious about fpga capabilities. I found the following project where apparently they instantiate a Rocket chip core and are able to run debian on it. Unfortunately there are no demo images or video, and i dont own a xilinx board, so i dont know what the system is capable of doing. Could one install a lightweight desktop environment or install packages using apt?
- Error when preparing a USB for use with an FPGA
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Running Hello World on a bare-metal RISC-V FPGA
But to save time, since you already have the Eugene Tarassov repo working running linux, you could look into modifying the bootrom for your needs. For example, you could take out all the stuff about loading files from SD card etc. and just include kprint.h and the bare minumum you need to print out over UART.
What are some alternatives?
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
linux-on-litex-vexriscv - Linux on LiteX-VexRiscv
picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU
picoMIPS - picoMIPS processor doing affine transformation
rocket-chip - Rocket Chip Generator
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
Rudi-RV32I - A rudimental RISCV CPU supporting RV32I instructions, in VHDL
neorv32-setups - 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
lxp32-cpu - A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
mempool - A 256-RISC-V-core system with low-latency access into shared L1 memory.