vivado-risc-v
mempool
vivado-risc-v | mempool | |
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6 | 2 | |
738 | 227 | |
- | 1.3% | |
7.5 | 9.0 | |
6 days ago | 6 days ago | |
Tcl | C | |
- | Apache License 2.0 |
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For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
vivado-risc-v
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Recommendations for RISC-V on FPGA
Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?
- How can I learn about RISC-V and use case? I want to do a project for begginers
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Open-source RISC-V CPU projects for contribution
For Xilinx FPGAs : https://github.com/eugene-tarassov/vivado-risc-v
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can one run one a linux distro like debian on an fpga?
I know it would run slowly, im not interested in performance, just curious about fpga capabilities. I found the following project where apparently they instantiate a Rocket chip core and are able to run debian on it. Unfortunately there are no demo images or video, and i dont own a xilinx board, so i dont know what the system is capable of doing. Could one install a lightweight desktop environment or install packages using apt?
- Error when preparing a USB for use with an FPGA
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Running Hello World on a bare-metal RISC-V FPGA
But to save time, since you already have the Eugene Tarassov repo working running linux, you could look into modifying the bootrom for your needs. For example, you could take out all the stuff about loading files from SD card etc. and just include kprint.h and the bare minumum you need to print out over UART.
mempool
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MemPool: Many-core image processor based on RISC-V with Shared L1 cache
I don't get it:
https://github.com/pulp-platform/mempool/blob/main/software/...
How is that mapping to cores happening? I see indexing by core id for the multiply but how does it magically end up running on a specific core? Magic compiler?
What are some alternatives?
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU
rt-thread - RT-Thread is an open source IoT real-time operating system (RTOS).
rocket-chip - Rocket Chip Generator
RVVM - The RISC-V Virtual Machine
Rudi-RV32I - A rudimental RISCV CPU supporting RV32I instructions, in VHDL
esp - Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
neorv32-setups - 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
esp32_usb_soft_host - ESP32 software USB host through general IO pins. We can connect up to 4 USB-LS HID (keyboard mouse joystick) devices simultaneously.
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.