vivado-risc-v VS chipyard

Hello. I'm looking into implementing RISC-V on an FPGA for a school project. The two repos I'm looking into using are the Ariane and RocketChip repos. Both look actively maintained, but RocketChip has more recent releases, and it's used by this other repo that creates a block design in Vivado with the RISC-V RTL. However, we would also like to be able to make changes to the core, and I'm afraid that scala/Chisel might be difficult to learn. Ariane looks like SystemVerilog while RocketChip is mostly Chisel. Does any have recommendations on which RISC-V repo would be good to use for a project?

For Xilinx FPGAs : https://github.com/eugene-tarassov/vivado-risc-v

I know it would run slowly, im not interested in performance, just curious about fpga capabilities. I found the following project where apparently they instantiate a Rocket chip core and are able to run debian on it. Unfortunately there are no demo images or video, and i dont own a xilinx board, so i dont know what the system is capable of doing. Could one install a lightweight desktop environment or install packages using apt?

But to save time, since you already have the Eugene Tarassov repo working running linux, you could look into modifying the bootrom for your needs. For example, you could take out all the stuff about loading files from SD card etc. and just include kprint.h and the bare minumum you need to print out over UART.

It's probably true that Chisel isn't right for industry -- Google tried it too for the TPU project and eventually went back to Verilog. That said, I think it's main win is that it is great from a research / open-source perspective.

Taking advantage of the functional nature of Chisel enables a set of generators called Chipyard [0] for things like cores, networking peripherals, neural network accelerators, etc. If you're focusing on exploring the design space of one particular accelerator and don't care too much about the rest of the chip, you can get a customized version of the RTL for the rest of your chip with ease. All the research projects in the lab benefit from code changes to the generators.

Chisel even enables undergraduate students (like me!) to tape out a chip on a modern-ish process node in just a semester, letting Chisel significantly reduce the amount of RTL we have to write. Most of the remaining time is spent working on the actual physical design process.

[0]: https://github.com/ucb-bar/chipyard

[1]: https://classes.berkeley.edu/content/2023-Spring-ELENG-194-0...

The repo in question is chipyard: https://github.com/ucb-bar/chipyard

Many companies do just write entire modern SoCs in straight Verilog (maybe with some autogenerated Verilog hacked in there) with no other major organization tools aside from the typical project management stuff. The load-store unit of a modern CPU alone easily exceeds 10k lines of Verilog. It's a similar thing as people who work with kernels—after all, the page table management code in a modern operating system like Linux is absolutely monstrous but still people are able to understand it well enough to be able to make the changes they need and get out.

If you are interested in other languages which hope to make this sort of stuff easier, I'd recommend taking a look at design productivity languages like Chisel and it's associated Chipyard [1], SpinalHDL [2], and Bluespec [3]. Each of these are meant to make defining extremely complex hardware more manageable for humans and there's a lot of interesting work going on right now with each of them.

[1] https://github.com/ucb-bar/chipyard

[2] https://github.com/SpinalHDL/SpinalHDL

[3] https://github.com/B-Lang-org/bsc