neorv32
upduino-projects
neorv32 | upduino-projects | |
---|---|---|
77 | 3 | |
1,433 | 6 | |
- | - | |
9.9 | 0.0 | |
2 days ago | over 1 year ago | |
C | VHDL | |
BSD 3-clause "New" or "Revised" License | GNU General Public License v3.0 only |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
neorv32
- An example of how to add the A ISA extension's LR/SC operations into an open-source architecture
- NEORV32 - A tiny, customizable and highly extensible MCU-class 32-bit RISC-V microcontroller-like SoC written in platform-independent VHDL
-
Recommendations for RISC-V on FPGA
How about NEORV32?
-
SUGGEST AN OPEN SOURCE RISC-V CORE DESIGNED IN VERILOG
GitHub - stnolting/neorv32: 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. this one is good but is written in VHDL though
-
RISCV CPU using PL on Pynq Z2 Development Board
NEORV32 is an open source soft core and very well documented. I would recommend you to take a look at it and play around a bit. And it is certainly possible to have a soft core running on only the PL side without PS interference.
- A tiny 1-Wire controller for FPGAs (in VHDL)
-
Anyone want to share some embedded projects they have done?
Maybe not a classic (whatever that means...) project, but I am working (together with others) on a RISC-V microcontroller for FPGAs: https://github.com/stnolting/neorv32
upduino-projects
- Does any one knows the vhdl code for (7,4) hamming code decoder?
- Using HOSC_CORE (Lattice Radiant, Ice40up5k, Synplify Pro, VHDL)
-
https://np.reddit.com/r/FPGA/comments/mro9hr/using_hosc_core_lattice_radiant_ice40up5k/gvsk3vg/
That'll give you the 48MHz clk. In the open source toolchain, you'd just change HSOSC to SB_HFOSC. More information about how to use the open source toolchain for VHDL (ghdl + yosys + icestorm + nextpnr) can be found in a few repos: - https://github.com/nobodywasishere/upduino-projects - https://github.com/controversial/es4 - https://github.com/YosysHQ/fpga-toolchain
What are some alternatives?
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
es4 - Code for Tufts ES4 Intro to Digital Electronics
linux-on-litex-vexriscv - Linux on LiteX-VexRiscv
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
picoMIPS - picoMIPS processor doing affine transformation
spi-fpga - SPI master and SPI slave for FPGA written in VHDL
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
fpga-toolchain - Multi-platform nightly builds of open source FPGA tools
lxp32-cpu - A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
forth-cpu - A Forth CPU and System on a Chip, based on the J1, written in VHDL
fpga-zynq - Support for Rocket Chip on Zynq FPGAs
ghdl - VHDL 2008/93/87 simulator