neorv32
ibex
neorv32 | ibex | |
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77 | 21 | |
1,429 | 1,250 | |
- | 1.9% | |
9.9 | 8.3 | |
1 day ago | 1 day ago | |
C | SystemVerilog | |
BSD 3-clause "New" or "Revised" License | Apache License 2.0 |
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neorv32
- An example of how to add the A ISA extension's LR/SC operations into an open-source architecture
- NEORV32 - A tiny, customizable and highly extensible MCU-class 32-bit RISC-V microcontroller-like SoC written in platform-independent VHDL
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Recommendations for RISC-V on FPGA
How about NEORV32?
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SUGGEST AN OPEN SOURCE RISC-V CORE DESIGNED IN VERILOG
GitHub - stnolting/neorv32: š„ļø A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. this one is good but is written in VHDL though
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RISCV CPU using PL on Pynq Z2 Development Board
NEORV32 is an open source soft core and very well documented. I would recommend you to take a look at it and play around a bit. And it is certainly possible to have a soft core running on only the PL side without PS interference.
- A tiny 1-Wire controller for FPGAs (in VHDL)
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Anyone want to share some embedded projects they have done?
Maybe not a classic (whatever that means...) project, but I am working (together with others) on a RISC-V microcontroller for FPGAs: https://github.com/stnolting/neorv32
ibex
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RISC-V support in Android just got a big setback
> Right now, most devices on the market do not support the C extension
This is not true and easily verifiable.
The C extension is defacto required, the only cores that don't support it are special purpose soft cores.
C extension in the smallest IP available core https://github.com/olofk/serv?tab=readme-ov-file
Supports M and C extensions https://github.com/YosysHQ/picorv32
Another sized optimized core with C extension support https://github.com/lowrisc/ibex
C extension in the 10 cent microcontroller https://www.wch-ic.com/products/CH32V003.html
This one should get your goat, it implements as much as it can using only compressed instructions https://github.com/gsmecher/minimax
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Major Changes at RISC-V Designer SiFive
We've had people consider Ibex for space applications, well verified and has a dual-core lockstep option: https://github.com/lowRISC/ibex.
An ETH Zurich team have done a triple core lockstep version for cubesats: https://www.theregister.com/2023/10/05/riscv_microcontroller...
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Hot Chips 2023: SiFiveās P870 Takes RISC-V Further
I definitely agree with the primary point, "building a chip that meets specfic requirements we got from the customer" is not easy and it what matters.
However, RISCV cores abound. In pretty much any computing language known to man with varying design trade-offs and capabilities. It's extremely difficult to differentiate at the RTL level at this time.
Here is a high quality, well documented, SystemVerilog version intended for embedded applications that I know has been included in multiple ASIC and FPGA designs successfully.
https://github.com/lowRISC/ibex
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Looking to work in Open Source Silicon and RISC-V? lowRISC is hiring DV and infrastructure engineers
lowRISC's (www.lowrisc.org) mission is to bring open source silicon to the hardware world and see it shipping in volume in commercial applications. We want to see open source silicon occupy a similar position to open source software (e.g. look at Linux, it's the default choice in many applications, we'd like open source silicon to be used for similar foundational technologies in the hardware world).
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How to use verilator to transfer a design with multiple files to a verilated model?
Here I will just use Ibex, a risc-v processor as an example, of which the repository is here: lowrisc_ibex. There are many files in this repository and I wonder which files I need given a specific configuration (for example, the configuration of "maxperf"), and how I can combine all the necessary files together, feed them to verilator and get its verilated model? I understand that only by going through this step will I acquire necessary C++ header files to write the testbench
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Ushering In a New Era for Open-Source Silicon Development (CEO of lowrisc , a non profit that develops open source hardware on why open source hardware failed in the past, and how lowrisc does things differently)
i think it might be worth it to post it here because lowrisc develops ibex (a open source risc-v core).
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What is to be gained from ISA convergence on all levels of computing?
Yeah but you can have both an open source (e.g. ibex) and closed source implementations for controllers (the open source one is free and you can improve it and even close its source so competitors won't benefit from your improvements) , and you can migrate from one supplier to another without spending a lot of money on migrating the software.
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synthesizing and using the Ibex RISC-V core
I am pretty new to RISC-V and open-source hardware and just began learning and working with them as part of my research. I searched about different models that have some credible documents and research done into them and decided I would try and use the ibex as the hardware language is easier for me to follow too.
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RISC-V Pushes into the Mainstream
Ibex is open source and has taped out - https://github.com/lowRISC/ibex
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RISC-V simulator
That said we used Spike as a reference simulator for verifying Ibex (RISC-V core I work on, https://github.com/lowRISC/ibex) and we run an extensive set of random programs through it comparing its execution to Ibex's and I've not come across any major issues.
What are some alternatives?
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
linux-on-litex-vexriscv - Linux on LiteX-VexRiscv
opentitan - OpenTitan: Open source silicon root of trust
picoMIPS - picoMIPS processor doing affine transformation
tomverbeure
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
riscv-isa-manual - RISC-V Instruction Set Manual
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
lowrisc-chip - The root repo for lowRISC project and FPGA demos.
lxp32-cpu - A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
amaranth - A modern hardware definition language and toolchain based on Python