neorv32-setups
picorv32
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neorv32-setups | picorv32 | |
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5 | 15 | |
52 | 2,770 | |
- | 2.8% | |
8.6 | 5.2 | |
6 days ago | about 1 month ago | |
VHDL | Verilog | |
BSD 3-clause "New" or "Revised" License | ISC License |
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neorv32-setups
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How to find the pin mapping for connecting Zybo Z7-20 or Nexyx A7 board to a computer over USB-JTAG?
Hello. In my project, I am trying to run NEORV32 processor in an FPGA. My plan is to perform debugging of the design over JTAG after running it on an FPGA. I currently have a Zybo Z7-20 and a Nexyx A7 board at hand. As per my understanding, for both of the boards, I need to find the board pins associated with JTAG and manually connect them through the constraint file. I was going through the reference manuals for both FPGAs but couldn't find the pins that need to be connected.
- RISC-V with AXI Peripheral
- Open-source RISC-V CPU projects for contribution
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A tiny and open-source (BSD) RISC-V SoC for (all!) FPGAs
and by "all" you of course mean some small Cyclones, Lattice ICE40s and Artix7 (see here)
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Risc-v rv32i softcore processor for Zybo-z7-10
There are some example setups here: https://github.com/stnolting/neorv32-setups
picorv32
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SPI PROTOCOL in FPGA
In contrast to most people here saying you NEED to spend money. I disagree with that. You can implement and simulate a SPI master/slave fully on your computer, no FPGA or other hardware required. There are simulation models for SPI peripherals you could use. For example: https://github.com/YosysHQ/picorv32/blob/master/picosoc/spiflash.v
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How many gates does a decent risc-v implementation take?
The Pico RV32 is pretty small, and can go as low as about 750 LUTs, with most features elided. I don't know how Xilinix LUTs translate to Lattice though.
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Open-source RISC-V CPU projects for contribution
Picorv32: https://github.com/YosysHQ/picorv32
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We ran a Unix-like OS (Xv6) on our home-built CPU with our home-built C compiler
There are loads of free RISC-V cores that you can read the source of and run on cheap FPGAs. Take a look at PicoRV32: https://github.com/YosysHQ/picorv32
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SUGGEST AN OPEN SOURCE RISC-V CORE DESIGNED IN VERILOG
picorv32 is written in Verilog.
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Minimax: a Compressed-First, Microcoded RISC-V CPU
In short: it works, though the implementation lacks the crystal clarity of FemtoRV32 and PicoRV32. The core is larger than SERV but has higher IPC and (very arguably) a more conventional implementation. The compressed instruction set is easier to expand into regular RV32I instructions than it is to execute directly.
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Apple to Move a Part of Its Embedded Cores to RISC-V
That is, reducing the number of LUT required to implement a CPU of a given ISA.
A basic RV32 CPU is down to 500-700 LUT.
https://github.com/YosysHQ/picorv32
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Designing a reasonable memory interface
I've bought a cheap FPGA board (Sipeed Tang Nano 9K) because I want to implement a little 8 or 16-bit CPU. The FPGA has plenty of BRAM for such a little CPU, so I wouldn't even need to implement an SPI controller initially, but I want to implement a von Neumann architecture, and was wondering if the only way of doing so using single port (or semi dual port) RAM would be to use 2 cycles or more for memory transfer operations (one for loading the instruction, one for executing the actual memory transfer), or if there was any technique that could be used to avoid this without having to implement instruction-level parallelism. Even if not, references to understandable code implementing a simple memory interface would be appreciated. I looked at PicoRV32 but couldn't really understand its inner workings.
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Risc-v rv32i softcore processor for Zybo-z7-10
Have you looked at PicoRV32? https://github.com/YosysHQ/picorv32
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Need help with implementing a media player using FPGAs ?
What I mean is that you use the FPGA fabric to implement a soft-core CPU, like MicroBlaze (Xilinx) or Nios II (Altera/Intel) or RISC-V or any other CPU you like. Then you can do the MP3 or WAV signal decoding in software, which will be orders of magnitude easier to do than to do it in hardware. For a media player, this is more than adequate.
What are some alternatives?
litex - Build your hardware, easily!
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
rocket-chip - Rocket Chip Generator
fpu - IEEE 754 floating point library in system-verilog and vhdl
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
neoTRNG - 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
wd65c02 - Cycle accurate FPGA implementation of various 6502 CPU variants
vivado-risc-v - Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
Projects - Ted Fried's MicroCore Labs Projects which include microsequencer-based FPGA cores and emulators for the 8088, 8086, 8051, 6502, 68000, Z80, Risc-V, and also Typewriter and EPROM Emulator projects. MCL51, MCL64, MCL65, MCL65+, MCL68, MCL86, MCL86+, MCL86jr, MCLR5, MCLZ8
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine