ice40_power
serv
| ice40_power | serv | |
|---|---|---|
| 2 | 20 | |
| 20 | 1,254 | |
| - | - | |
| 0.0 | 7.6 | |
| over 3 years ago | 23 days ago | |
| Verilog | Verilog | |
| MIT License | ISC License |
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ice40_power
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iCE40 power consumption question
You can probably extrapolate from the numbers here.
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Using an FPGA for low-power device with fast image acquisition
Aside from the points that /u/captain_wiggles_ pointed out, this is an application which ice40 FPGAs were actually designed for. They are low power (example) and have some features specifically designed for video applications, such as (sub)LVDS inputs and "outputs." Depending on your specs, one of these FPGAs could be a good choice (and you get a nice FOSS toochain as a bonus).
serv
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RISC-V support in Android just got a big setback
> Right now, most devices on the market do not support the C extension
This is not true and easily verifiable.
The C extension is defacto required, the only cores that don't support it are special purpose soft cores.
C extension in the smallest IP available core https://github.com/olofk/serv?tab=readme-ov-file
Supports M and C extensions https://github.com/YosysHQ/picorv32
Another sized optimized core with C extension support https://github.com/lowrisc/ibex
C extension in the 10 cent microcontroller https://www.wch-ic.com/products/CH32V003.html
This one should get your goat, it implements as much as it can using only compressed instructions https://github.com/gsmecher/minimax
- SERV – The SErial RISC-V CPU
- SERV: A bit-serial RISC-V core
- SERV – open-source Tiny SErial RISC-V CPU
- How many LUT for an 8 bit CPU?
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Minimax: a Compressed-First, Microcoded RISC-V CPU
In short: it works, though the implementation lacks the crystal clarity of FemtoRV32 and PicoRV32. The core is larger than SERV but has higher IPC and (very arguably) a more conventional implementation. The compressed instruction set is easier to expand into regular RV32I instructions than it is to execute directly.
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Apple to Move a Part of Its Embedded Cores to RISC-V
https://github.com/olofk/serv
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I have created a Reddit community about PicoBlaze soft processor...
As for the size advantage: this mattered more when LUTs were precious and when PicoBlaze's competition was either similarly unorthodox (J1 Forth CPU) or several times larger (MicroBlaze). Nowadays, there are very small RISC-V cores like FemtoRV32 Quark or SERV. RISC-V benefits from mainstream open-source tooling and has momentum that's hard to beat.
- Microchip to develop 12-core RISC-V processor for NASA
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RISC-V announces first new specifications of 2022 adding to 16 ratified in 2021
The RISC-V spec does allow non-trapping behavior and SeRV in particular has non-trapping behavior, which is an important part of how it can fit into 200 4-input LUTs.
https://github.com/olofk/serv#good-to-know
What are some alternatives?
riscv - RISC-V CPU Core (RV32IM)
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
a2o - The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, using out-of-order execution (register renaming, reservation stations, completion buffer) and a store queue. It is now being updated for compliancy and integration into open projects.
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
IronOS - Open Source Soldering Iron firmware
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
neo430 - :computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA
edalize - An abstraction library for interfacing EDA tools
riscv_verilator_model - RISCV model for Verilator/FPGA targets
zipversa - A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure
minimax - Minimax: a Compressed-First, Microcoded RISC-V CPU