fusesoc_template
edalize
| fusesoc_template | edalize | |
|---|---|---|
| 1 | 4 | |
| 15 | 655 | |
| - | - | |
| 1.8 | 7.5 | |
| over 3 years ago | 11 days ago | |
| Python | Python | |
| - | BSD 2-clause "Simplified" License |
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fusesoc_template
-
Vivado dark mode
I made a repo on getting started: https://github.com/E4tHam/fusesoc_template
edalize
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Dropping EDA-GUI's 101
Check out FuseSoC: https://github.com/olofk/fusesoc which can handle Vivado builds for you (utilizing edalize: https://github.com/olofk/edalize) along with some nice package management. It can run against multiple tools so you can also get it to build simulations using Verilator or a commercial EDA tool if you have access to them.
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Introduction to FPGAs
Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
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Compiling Code into Silicon
This reminds me very much of edalize[1], which does something very similar.
[1]: https://github.com/olofk/edalize
- Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
What are some alternatives?
verilog_template - A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
sphinxcontrib-hdl-diagrams - Sphinx Extension which generates various types of diagrams from Verilog code.
freepdk-45nm - ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
RapidStream - This is a personal archive. Please refer to github.com/UCLA-VAST/RapidStream
icestudio - :snowflake: Visual editor for open FPGA boards
icicle - 32-bit RISC-V system on chip for iCE40 FPGAs
rggen - Code generation tool for control and status registers
nmigen
serv - SERV - The SErial RISC-V CPU
hdl_checker - Repurposing existing HDL tools to help writing better code
apio - :seedling: Open source ecosystem for open FPGA boards