fusesoc_template
Example of how to get started with olofk/fusesoc. (by sifferman)
RapidStream
This is a personal archive. Please refer to github.com/UCLA-VAST/RapidStream (by Licheng-Guo)
fusesoc_template | RapidStream | |
---|---|---|
1 | 2 | |
15 | 10 | |
- | - | |
1.8 | 0.0 | |
over 3 years ago | over 2 years ago | |
Python | Python | |
- | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
fusesoc_template
Posts with mentions or reviews of fusesoc_template.
We have used some of these posts to build our list of alternatives
and similar projects.
-
Vivado dark mode
I made a repo on getting started: https://github.com/E4tHam/fusesoc_template
RapidStream
Posts with mentions or reviews of RapidStream.
We have used some of these posts to build our list of alternatives
and similar projects.
-
Drumroll! 5-7x faster compilation for Xilinx.
RapidStream
-
Ultra-Fast Parallel Placement and Routing for Vivado HLS Dataflow Designs!
Please take a look at our repo, RapidStream, and please we appreciate it if you can give a star⭐️ to our repo if you like the idea! https://github.com/Licheng-Guo/RapidStream
What are some alternatives?
When comparing fusesoc_template and RapidStream you can also consider the following projects:
verilog_template - A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.
entangle - A lightweight (serverless) native python parallel processing framework based on simple decorators and call graphs.
sphinxcontrib-hdl-diagrams - Sphinx Extension which generates various types of diagrams from Verilog code.
edalize - An abstraction library for interfacing EDA tools
icicle - 32-bit RISC-V system on chip for iCE40 FPGAs
nmigen