fusesoc_template
sphinxcontrib-hdl-diagrams
| fusesoc_template | sphinxcontrib-hdl-diagrams | |
|---|---|---|
| 1 | 2 | |
| 12 | 51 | |
| - | - | |
| 1.8 | 5.7 | |
| almost 3 years ago | 8 months ago | |
| Python | Python | |
| - | Apache License 2.0 |
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fusesoc_template
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Vivado dark mode
I made a repo on getting started: https://github.com/E4tHam/fusesoc_template
sphinxcontrib-hdl-diagrams
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Is there any software I can use to transform state machines in VHDL into drawings?
Well, you can convert VHDL into Verilog using Icarus Verilog, and then you can draw a logic gate diagram (.svg file) to visualize your code using this: https://github.com/SymbiFlow/sphinxcontrib-hdl-diagrams
- Systemverilog / verilog functional editor not like vivado
What are some alternatives?
verilog_template - A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.
verilator - Verilator open-source SystemVerilog simulator and lint system
RapidStream - This is a personal archive. Please refer to github.com/UCLA-VAST/RapidStream
sane_tikz - Reconquer the canvas: beautiful Tikz figures without clunky Tikz code
edalize - An abstraction library for interfacing EDA tools
cocotb-bus - Pre-packaged testbenching tools and reusable bus interfaces for cocotb
amaranth - A modern hardware definition language and toolchain based on Python
sphinx-tabs - Tabbed views for Sphinx
gdscript-docs-maker - Create documentation and class references from your Godot GDScript code
docs - Documentation site
sphinx-readme - Generate Beautiful reStructuredText README.rst for GitHub, PyPi, GitLab, BitBucket
tang-doc - Documentation for Lichee Tang