Is there any software I can use to transform state machines in VHDL into drawings?

• sphinxcontrib-hdl-diagrams

  2 50 5.7 Python

  Sphinx Extension which generates various types of diagrams from Verilog code.

  

Well, you can convert VHDL into Verilog using Icarus Verilog, and then you can draw a logic gate diagram (.svg file) to visualize your code using this: https://github.com/SymbiFlow/sphinxcontrib-hdl-diagrams

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  www.influxdata.com sponsored

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