fusesoc
Package manager and build abstraction tool for FPGA/ASIC development (by olofk)
ghdl
VHDL 2008/93/87 simulator (by ghdl)
Our great sponsors
| fusesoc | ghdl | |
|---|---|---|
| 12 | 26 | |
| 1,118 | 2,210 | |
| - | 2.9% | |
| 7.3 | 9.8 | |
| 18 days ago | 10 days ago | |
| Python | VHDL | |
| BSD 2-clause "Simplified" License | GNU General Public License v3.0 only |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
fusesoc
Posts with mentions or reviews of fusesoc.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-03-28.
-
fusesoc VS vextproj - a user suggested alternative
2 projects | 28 Mar 2024
-
Introduction to FPGAs
Check out https://github.com/olofk/fusesoc. It gives you a command line build flow that can drive Vivado (along with many other eda tools via edalize https://github.com/olofk/edalize) without having to touch the GUI (though you might want it for programming the board, though FuseSoC can do that too).
-
CI/CD for FPGA builds
Check out FuseSoC: https://github.com/olofk/fusesoc it can run Vivado builds for you (as well as many other tools). It may be less work to get FuseSoC setup then work out a CLI Vivado batch flow from scratch.
-
Besides misterFPGA what else can I play with on a DE10-nano?
Also, the FuseSOC and LiteX projects both support the DE10 nano, and can be used to roll your own custom SOCs with RISC-V or OpenRISC cores.
-
Why isn't all verification work done in Python
Integration with the dependency and build tool I use (FuseSoc) is clumsy.
-
Using Python with Vivado Projects
The "fusesoc" project may be of interest to you.
-
Any recommendations for an RTL "standard library"?
FuseSoC is an RTL package manager. It will automatically download the latest versions of required components when you build. It also comes with a bunch of great options for components here:
-
What should a modern IP library look like?
Have to correct this slightly: I just heard of my first HDL package manager in this thread. FuseSOC: https://github.com/olofk/fusesoc - Thanks u/gac_cag!
- Olof Kindgren on LinkedIn: We have a new world record! 6000 RISC-V cores in a single chip!
- Industry development process?
ghdl
Posts with mentions or reviews of ghdl.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-03-30.
-
GHDL on mac m1
I downloaded https://github.com/ghdl/ghdl/releases/download/v3.0.0/ghdl-macos-11-mcode.tgz and extracted it to home directory ~.
- How to compile ghdl
-
Is the VHDL standard library not publicly available?
The body is here.
-
Help on trying to find a FOSS solution to replace Quartus in my class.
GHDL + gtkwave
-
If someone is good at programming languages like C, will they be good at description languages like VHDL?
Also, VHDL has its roots in Ada, not Pascal. (In fact, the ghdl simulation tool is written in Ada.)
-
What is the netlist file format?
If the goal is simulation, the output of the process is something that can be processed by a standard compiler (like gcc or llvm) or executed by a pseudocode interpreter. See, for example, what is done by ghdl.
-
Converting VHDL to Verilog using GHDL
Maybe you could try to minimize your example to a MWE (minimum working example that demonstrates the issue) and then do a bug report against GHDL at https://github.com/ghdl/ghdl/issues
Try a question here: https://github.com/ghdl/ghdl/issues . I have only used GHDL for VHDL, and it worked well for what I was doing with it, but the creator/chief maintainer(?) (Tristan Gingold) should be able to set your issue straight in a short while, and he is pretty active on github.
-
Trouble with GHDL and GCC
Find something newer here.
-
ghdl, how to include math_real?
replying to myself: I just installed this nightly on a Win10 box and it seems to "work" based on minimal tests. Note that you need to install MinGW.
What are some alternatives?
When comparing fusesoc and ghdl you can also consider the following projects:
litex - Build your hardware, easily!
logisim-evolution - Digital logic design tool and simulator
edalize - An abstraction library for interfacing EDA tools
rust_hdl
opentitan - OpenTitan: Open source silicon root of trust
vunit - VUnit is a unit testing framework for VHDL/SystemVerilog
cocotb - cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
awesome-ada - A curated list of awesome resources related to the Ada and SPARK programming language
teroshdl-documenter-demo - This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.
gtkwave - GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.
rocket-chip - Rocket Chip Generator
VHDL-Guide - VHDL Guide