fpga_riscv_cpu
riscv
fpga_riscv_cpu | riscv | |
---|---|---|
1 | 2 | |
8 | 1,040 | |
- | - | |
1.1 | 1.8 | |
about 1 year ago | over 2 years ago | |
Verilog | Verilog | |
MIT License | BSD 3-clause "New" or "Revised" License |
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fpga_riscv_cpu
riscv
-
Ultraembedded RISCV Module
I have been trying to execute some instructions to the ultraembedded riscv module https://github.com/ultraembedded/riscv
- I made my own silicon chip: Project Silicon Rider
What are some alternatives?
RISC-V - Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
biriscv - 32-bit Superscalar RISC-V CPU
friscv - RISCV CPU implementation in SystemVerilog
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Hazard3 - 3-stage RV32IMACZb* processor with debug
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
zipcpu - A small, light weight, RISC CPU soft core
Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog
uhd - The USRP™ Hardware Driver Repository
riscv-cores-list - RISC-V Cores, SoC platforms and SoCs
livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
airisc_core_complex - Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.