f4pga-examples
Example designs showing different ways to use F4PGA toolchains. (by chipsalliance)
darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night! (by darklife)
| f4pga-examples | darkriscv | |
|---|---|---|
| 1 | 3 | |
| 260 | 1,892 | |
| 0.8% | 1.7% | |
| 4.3 | 6.3 | |
| about 1 month ago | 16 days ago | |
| Verilog | Verilog | |
| Apache License 2.0 | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
f4pga-examples
Posts with mentions or reviews of f4pga-examples.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-09-28.
darkriscv
Posts with mentions or reviews of darkriscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-08-20.
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As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?
This guy here has designed his 2 stage RISC-V in just one right: https://github.com/darklife/darkriscv.
- Are there any dual-GBE, PoE-capable SBCs?
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Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
What are some alternatives?
When comparing f4pga-examples and darkriscv you can also consider the following projects:
zipcpu - A small, light weight, RISC CPU soft core
biriscv - 32-bit Superscalar RISC-V CPU