RISC-V VS riscv

Compare RISC-V vs riscv and see what are their differences.

RISC-V

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension (by AngeloJacobo)
risc-v Verilog Rv32i rv32 Cpu Riscv 5-stage-pipeline Formal Verification
Source Code
Suggest alternative
Edit details

riscv

RISC-V CPU Core (RV32IM) (by ultraembedded)
risc-v Cpu Verilog Fpga Verilator Rv32im Rv32i riscv-linux pipeline-processor Asic Verification
Source Code
Suggest alternative
Edit details
InfluxDB - Power Real-Time Data Analytics at Scale
Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
www.influxdata.com
featured
SaaSHub - Software Alternatives and Reviews
SaaSHub helps you find the best software and product alternatives
www.saashub.com
featured
RISC-V riscv
1 2
45 1,040
- -
7.6 1.8
5 months ago over 2 years ago
Verilog Verilog
MIT License BSD 3-clause "New" or "Revised" License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

RISC-V

Posts with mentions or reviews of RISC-V. We have used some of these posts to build our list of alternatives and similar projects.

riscv

Posts with mentions or reviews of riscv. We have used some of these posts to build our list of alternatives and similar projects.

What are some alternatives?

When comparing RISC-V and riscv you can also consider the following projects:

biriscv - 32-bit Superscalar RISC-V CPU

fpga_riscv_cpu - fpga verilog risc-v rv32i cpu

openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

zipcpu - A small, light weight, RISC CPU soft core

Toast-RV32i - Pipelined RISC-V RV32I Core in Verilog

uhd - The USRP™ Hardware Driver Repository

riscv-cores-list - RISC-V Cores, SoC platforms and SoCs

livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

RISC-V vs biriscv riscv vs biriscv RISC-V vs fpga_riscv_cpu riscv vs openlane RISC-V vs neorv32 riscv vs darkriscv RISC-V vs darkriscv riscv vs zipcpu riscv vs Toast-RV32i riscv vs uhd riscv vs riscv-cores-list riscv vs livehd